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Geometry scaling due to technology evolution as well as Vcc scaling lead to failures in large SRAM arrays such as caches. Faulty bits can be tolerated from the average performance perspective, but make critical realtime embedded systems non time-analyzable or worstcase execution time (WCET) estimations unacceptably large.
This paper proposes a mechanism to tolerate faulty bits in caches while still providing safe and tightWCET. Our solution is based on adapting structures such as the victim cache, cache eviction buffers or miss state handle registers to serve as replacement for faulty cache storage. We show how modest modifications in the hardware help providing safe and tight WCET on the face of permanent faulty bits with negligible impact in power
CitationAbella, J. [et al.]. RVC: A mechanism for time-analyzable real-time processors with faulty caches. A: International Conference on High Performance Embedded Architectures & Compilers (HiPEAC). "6th International Conference on High Performance and Embedded Architectures and Compilers". 2011, p. 97-106.
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