Nowadays, there is a clear trend in industry towards employing the growing amount of transistors on chip in replicating execution cores (CMP), where each core is Simultaneous Multithreading (SMT). State-of-the-art high-performance processors like the IBM
POWER5 and POWER6 corroborate this CMP+SMT
trend. Within each SMT core any of the well-known SMT mechanisms may be applied to face SMT related challenges. Among them, probably the most important issue in an SMT execution pipeline concerns the In-struction Fetch (IFetch) Policy. The FLUSH IFetch
Policy represents a choice for throughput-oriented scenarios. It handles L2 cache misses in order to avoid hardware resource monopolization by any given execution Thread; involving an additional energy cost via instruction refetching. However, the new constraints imposed by the CMP+SMT scenario may a ect wellknown SMT mechanisms, like the FLUSH mechanism.
CitationAcosta, C. A. [et al.]. MFLUSH: handling long-latency loads in SMT on-chip multiprocessors. A: International Conference on Parallel Processing. "37th International Conference on Parallel Processing, ICPP '08.". Portland: IEEE Computer Society Publications, 2008, p. 173-181.
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