Electromagnetic compatibility of CMOS circuits along the lifetime

Abstract

The continuous scaling of CMOS circuits has set the MOSFET transistor in the nanoelectronic era. In this context, the functionality and complexity of integrated circuits (ICs) are growing up. However, the operation voltage has been continuously reduced. The higher complexity of ICs has allowed including electronic systems in a lot of safety critical applications (i.e., automotive, aeronautics and/or medical applications). Therefore, the functionality of these electronic equipments must be assured and the risk of electromagnetic interference (EMI) must be reduced during their lifetime. Nowadays, circuits’ robustness to electromagnetic interference is checked in a burn-in component, without taking into account the impact of the natural devices’ aging. However, shrunk dimensions imply the appearance of several wear out mechanisms, which can limit the functionality of the circuits and modify their electromagnetic performance. Therefore, the time dependence of electromagnetic behaviour, which is known as Electromagnetic Robustness or Electromagnetic Reliability (EMR), should be evaluated. The switching noise is probably one of the main EMC emission problems in CMOS circuits. It is know that wear out mechanism affects the switching behaviour of CMOS circuits. Therefore, some effects on EMC performance of these circuits should be expected. In this work, the switching noise behaviour or CMOS circuits under one of the most important reliability problems are analysed by means of electrical simulation. In order to do that, a characterization of wear out mechanism on single MOSFET is presented and modelled. The results show a reduction on the frequency switching noise emission in circuits subjected to wear out, due to the reduction of the drain current of MOSFET.