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ITCA: inter-task conflict-aware CPU accounting for CMPs
| dc.contributor.author | Luque, Carlos |
| dc.contributor.author | Moretó Planas, Miquel |
| dc.contributor.author | Cazorla Almeida, Francisco Javier |
| dc.contributor.author | Gioiosa, Roberto |
| dc.contributor.author | Buyuktosunoglu, Alper |
| dc.contributor.author | Valero Cortés, Mateo |
| dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
| dc.date.accessioned | 2011-04-05T10:49:56Z |
| dc.date.available | 2011-04-05T10:49:56Z |
| dc.date.created | 2009 |
| dc.date.issued | 2009 |
| dc.identifier.citation | Luque, C. [et al.]. ITCA: inter-task conflict-aware CPU accounting for CMPs. A: International Conference on Parallel Architectures and Compilation Techniques. "The Eighteenth International Conference on Parallel Architectures and Compilation Techinques". Raleigh, North Carolina: IEEE Computer Society Publications, 2009, p. 203-213. |
| dc.identifier.isbn | 978-0-7695-3771-9 |
| dc.identifier.uri | http://hdl.handle.net/2117/12246 |
| dc.description | Chip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism from an application. CMPs introduce complexities when accounting CPU utilization. This is due to the fact that the progress done by an application during an interval of time highly depends on the activity of the other applications it is co-scheduled with. In this paper, we identify how an inaccurate measurement of the CPU utilization affects several key aspects of the system like the application scheduling or the charging mechanism in data centers. We propose a new hardware CPU accounting mechanism to improve the accuracy when measuring the CPU utilization in CMPs and compare it with the previous accounting mechanisms. Our results show that currently known mechanisms lead to a 19% average error when it comes to CPU utilization accounting. Our proposal reduces this error to less than 1% in a modeled 4-core processor system. |
| dc.format.extent | 11 p. |
| dc.language.iso | eng |
| dc.publisher | IEEE Computer Society Publications |
| dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| dc.subject.lcsh | Multiprocessors |
| dc.subject.lcsh | Cache memory |
| dc.subject.lcsh | System design |
| dc.subject.other | Cycle accounting |
| dc.subject.other | Chip-Multiprocessor |
| dc.subject.other | Cache partitioning algorithms |
| dc.subject.other | Fairness |
| dc.subject.other | ATD |
| dc.title | ITCA: inter-task conflict-aware CPU accounting for CMPs |
| dc.type | Conference report |
| dc.subject.lemac | Multiprocessadors |
| dc.subject.lemac | Memòria cau |
| dc.subject.lemac | Disseny de sistemes |
| dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
| dc.identifier.doi | 10.1109/PACT.2009.33 |
| dc.rights.access | Restricted access - publisher's policy |
| local.identifier.drac | 2396657 |
| dc.description.version | Postprint (published version) |
| local.citation.author | Luque, C.; Moretó, M.; Cazorla, F.; Gioiosa, R.; Buyuktosunoglu, A.; Valero, M. |
| local.citation.contributor | International Conference on Parallel Architectures and Compilation Techniques |
| local.citation.pubplace | Raleigh, North Carolina |
| local.citation.publicationName | The Eighteenth International Conference on Parallel Architectures and Compilation Techinques |
| local.citation.startingPage | 203 |
| local.citation.endingPage | 213 |