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Transistor sizing analysis of regular fabrics
dc.contributor.author | Marranghello, Felipe S. |
dc.contributor.author | Dal Bem, Vinicius |
dc.contributor.author | Reis, André Inácio |
dc.contributor.author | Ribas, Renato P. |
dc.contributor.author | Moll Echeto, Francisco de Borja |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2011-03-29T12:46:59Z |
dc.date.available | 2011-03-29T12:46:59Z |
dc.date.created | 2011 |
dc.date.issued | 2011 |
dc.identifier.citation | Marranghello, F. [et al.]. Transistor sizing analysis of regular fabrics. A: Exploiting Regularity in the Design of IPs, Architectures and Platforms. "1st Workshop on Exploiting Regularity in the Design of IPs, Architectures and Platforms". Como: 2011, p. 235-242. |
dc.identifier.isbn | 978-3-8007-3333-0 |
dc.identifier.uri | http://hdl.handle.net/2117/12138 |
dc.description.abstract | This paper presents an extensive transistor sizing analysis for regular transistor fabrics. Several evaluation methods have been exploited, such as DC simulations, ring oscillators and single-gate open chain structures. Different design aspects are addressed taking into account stacked transistors, cells with drive strengths and circuit critical paths. The performance degradation of using regular fabrics in comparison to standard cells is naturally expected, but it is quite important to evaluate the dimension of such impact. The results were obtained for predictive PTM45 CMOS parameters, and the conclusions can be easily extrapolated to other technology nodes and fabrication processes |
dc.format.extent | 8 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject.lcsh | Resolution Enhancement Techniques |
dc.subject.lcsh | Regular Transistor Fabric |
dc.subject.lcsh | Electronic engineering |
dc.title | Transistor sizing analysis of regular fabrics |
dc.type | Conference report |
dc.subject.lemac | Electrònica |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.rights.access | Open Access |
local.identifier.drac | 5379994 |
dc.description.version | Postprint (published version) |
local.citation.author | Marranghello, F.; Dal Bem, V.; Reis, A.; Ribas, R.; Moll, F. |
local.citation.contributor | Exploiting Regularity in the Design of IPs, Architectures and Platforms |
local.citation.pubplace | Como |
local.citation.publicationName | 1st Workshop on Exploiting Regularity in the Design of IPs, Architectures and Platforms |
local.citation.startingPage | 235 |
local.citation.endingPage | 242 |