This paper presents an extensive transistor sizing analysis for regular transistor fabrics. Several evaluation methods
have been exploited, such as DC simulations, ring oscillators and single-gate open chain structures. Different design
aspects are addressed taking into account stacked transistors, cells with drive strengths and circuit critical paths. The
performance degradation of using regular fabrics in comparison to standard cells is naturally expected, but it is quite
important to evaluate the dimension of such impact. The results were obtained for predictive PTM45 CMOS
parameters, and the conclusions can be easily extrapolated to other technology nodes and fabrication processes
CitationMarranghello, F. [et al.]. Transistor sizing analysis of regular fabrics. A: Exploiting Regularity in the Design of IPs, Architectures and Platforms. "1st Workshop on Exploiting Regularity in the Design of IPs, Architectures and Platforms". Como: 2011, p. 235-242.
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