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VCTA: A Via-Configurable Transistor Array regular fabric
dc.contributor.author | Pons Solé, Marc |
dc.contributor.author | Moll Echeto, Francisco de Borja |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.author | Abella Ferrer, Jaume |
dc.contributor.author | Vera Rivera, Francisco Javier |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2011-02-14T12:59:45Z |
dc.date.available | 2011-02-14T12:59:45Z |
dc.date.created | 2010 |
dc.date.issued | 2010 |
dc.identifier.citation | Pons, M. [et al.]. VCTA: A Via-Configurable Transistor Array regular fabric. A: VLSI System on Chip Conference. "18th IEEE/IFIP VLSI System on Chip Conference (VLSI-SoC)". Madrid: IEEE Computer Society Publications, 2010, p. 335-340. |
dc.identifier.isbn | 978-1-4244-6469-2 |
dc.identifier.uri | http://hdl.handle.net/2117/11358 |
dc.description.abstract | Layout regularity is introduced progressively by integrated circuit manufacturers to reduce the increasing systematic process variations in the deep sub-micron era. In this paper we focus on a scenario where layout regularity must be pushed to the limit to deal with severe systematic process variations in future technology nodes. With this objective, we propose and evaluate a new regular layout style called Via-Configurable Transistor Array (VCTA) that maximizes regularity at device and interconnect levels. In order to assess VCTA maximum layout regularity tradeoffs, we implement 32-bit adders in the 90 nm technology node for VCTA and compare them with implementations that make use of standard cells. For this purpose we study the impact of photolithography proximity and coma effects on channel length variations, and the impact of shallow trench isolation mechanical stress on threshold voltage variations. We demonstrate that both variations, that are important sources of energy and delay circuit variability, are minimized through VCTA regularity. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.publisher | IEEE Computer Society Publications |
dc.subject.lcsh | Delay lines |
dc.subject.lcsh | Integrated circuit layout |
dc.subject.lcsh | Photolithography |
dc.subject.lcsh | Proximity effect (lithography) |
dc.subject.lcsh | Via-Configurable Transistor Array |
dc.subject.lcsh | VCTA |
dc.title | VCTA: A Via-Configurable Transistor Array regular fabric |
dc.type | Conference report |
dc.subject.lemac | Litografia |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/VLSISOC.2010.5642683 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5642683 |
dc.rights.access | Open Access |
local.identifier.drac | 4947796 |
dc.description.version | Postprint (published version) |
local.citation.author | Pons, M.; Moll, F.; Rubio, J.; Abella, J.; Vera, F.; González, A. |
local.citation.contributor | VLSI System on Chip Conference |
local.citation.pubplace | Madrid |
local.citation.publicationName | 18th IEEE/IFIP VLSI System on Chip Conference (VLSI-SoC) |
local.citation.startingPage | 335 |
local.citation.endingPage | 340 |