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dc.contributor.authorPons Solé, Marc
dc.contributor.authorMoll Echeto, Francisco de Borja
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorVera Rivera, Francisco Javier
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2011-02-14T12:59:45Z
dc.date.available2011-02-14T12:59:45Z
dc.date.created2010
dc.date.issued2010
dc.identifier.citationPons, M. [et al.]. VCTA: A Via-Configurable Transistor Array regular fabric. A: VLSI System on Chip Conference. "18th IEEE/IFIP VLSI System on Chip Conference (VLSI-SoC)". Madrid: IEEE Computer Society Publications, 2010, p. 335-340.
dc.identifier.isbn978-1-4244-6469-2
dc.identifier.urihttp://hdl.handle.net/2117/11358
dc.description.abstractLayout regularity is introduced progressively by integrated circuit manufacturers to reduce the increasing systematic process variations in the deep sub-micron era. In this paper we focus on a scenario where layout regularity must be pushed to the limit to deal with severe systematic process variations in future technology nodes. With this objective, we propose and evaluate a new regular layout style called Via-Configurable Transistor Array (VCTA) that maximizes regularity at device and interconnect levels. In order to assess VCTA maximum layout regularity tradeoffs, we implement 32-bit adders in the 90 nm technology node for VCTA and compare them with implementations that make use of standard cells. For this purpose we study the impact of photolithography proximity and coma effects on channel length variations, and the impact of shallow trench isolation mechanical stress on threshold voltage variations. We demonstrate that both variations, that are important sources of energy and delay circuit variability, are minimized through VCTA regularity.
dc.format.extent6 p.
dc.language.isoeng
dc.publisherIEEE Computer Society Publications
dc.subject.lcshDelay lines
dc.subject.lcshIntegrated circuit layout
dc.subject.lcshPhotolithography
dc.subject.lcshProximity effect (lithography)
dc.subject.lcshVia-Configurable Transistor Array
dc.subject.lcshVCTA
dc.titleVCTA: A Via-Configurable Transistor Array regular fabric
dc.typeConference report
dc.subject.lemacLitografia
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/VLSISOC.2010.5642683
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5642683
dc.rights.accessOpen Access
local.identifier.drac4947796
dc.description.versionPostprint (published version)
local.citation.authorPons, M.; Moll, F.; Rubio, J.; Abella, J.; Vera, F.; González, A.
local.citation.contributorVLSI System on Chip Conference
local.citation.pubplaceMadrid
local.citation.publicationName18th IEEE/IFIP VLSI System on Chip Conference (VLSI-SoC)
local.citation.startingPage335
local.citation.endingPage340


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