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Lithography aware regular cell design based on a predictive technology model
dc.contributor.author | Gómez Fernández, Sergio |
dc.contributor.author | Moll Echeto, Francisco de Borja |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2011-01-25T14:07:25Z |
dc.date.available | 2011-01-25T14:07:25Z |
dc.date.created | 2010-12 |
dc.date.issued | 2010-12 |
dc.identifier.citation | Gómez, S.; Moll, F. Lithography aware regular cell design based on a predictive technology model. "Journal of low power electronics", Desembre 2010, vol. 6, núm. 4, p. 588-600. |
dc.identifier.issn | 1546-1998 |
dc.identifier.uri | http://hdl.handle.net/2117/11201 |
dc.description.abstract | As semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated that layout regularity reduces the increasing impact of process variations on circuit performance and reliability. The aim of this paper is to present the layout design of a regular cell based on 1-D elements which reduces lithography perturbations (ALARC). We depict several undesirable lithography effects and how these distortions determine several layout parameters in order to achieve the required line-pattern resolution. Furthermore, it is shown how the measurement of leakage power consumption based on ideal layout is not a precise metric to evaluate circuit performance, especially for low power designs. Finally, the impact of lithography patterns on delay and leakage consumption of a typical cell is provided. |
dc.format.extent | 13 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència |
dc.subject.lcsh | Design for Manufacturability |
dc.subject.lcsh | DFM |
dc.subject.lcsh | Lithography simulation |
dc.title | Lithography aware regular cell design based on a predictive technology model |
dc.type | Article |
dc.subject.lemac | Manufacturabilitat |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://openurl.ingenta.com/content?genre=article&issn=1546-1998&volume=6&issue=4&spage=588&epage=600 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 4476105 |
dc.description.version | Postprint (published version) |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/FP7/248538/EU/SYNthesis using Advanced Process Technology Integrated in regular Cells, IPs, architectures, and design platforms/SYNAPTIC |
local.citation.author | Gómez, S.; Moll, F. |
local.citation.publicationName | Journal of low power electronics |
local.citation.volume | 6 |
local.citation.number | 4 |
local.citation.startingPage | 588 |
local.citation.endingPage | 600 |
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