The temperature at surface of a silicon die depends
on the activity of the circuits placed on it. In this paper, it is
analyzed how Process, Voltage and Temperature (PVT) variations
affect simultaneously some figures of merit (FoM) of some digital
and analog circuits and the power dissipated by such circuits. It is
shown that in some cases, a strong correlation exists between the
variation of the circuit FoM and the variation of the dissipated
power. Since local temperature increase at the silicon surface
close to the circuit linearly depends on dissipated power, the
results show that temperature can be considered as an observable
magnitude for CMOS technology variability monitoring.
CitationAltet, J. [et al.]. On evaluating temperature as observable for CMOS technology variability. A: European workshop on CMOS Variability. "1st IEEE European Workshop on CMOS Variability". Montpellier: 2010, p. 1-6.
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