Performance impact of a slower main memory: a case study of STT-MRAM in HPC

Abstract

Memory systems are major contributors to the deployment and operational costs of large-scale HPC clusters [1][2][3], as well as one of the most important design parameters that significantly affect system performance. In addition, scaling of the DRAM technology and expanding the main memory capacity increases the probability of DRAM errors that have already become a common source of system failures in the field. It is questionable whether mature DRAM technology will meet the needs of next-generation main memory systems. So, significant effort is invested in research and development of novel memory technologies. A potential candidate for replacing DRAM is Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM). In this paper, we explore whether STT-MRAM is a good candidate for HPC main memory systems. To that end, we simulate and analyze performance of production HPC applica-tions running on large-scale clusters with STT-MRAM main memory, and compare the results with DRAM. Our results show that, despite being 20% slower than DRAM at the device level, STT-MRAM main memory delivers performance comparable to DRAM — for most of the applications under study, STT-MRAM introduces a slowdown below 1%.