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dc.contributor.authorSantana Jaria, Oliverio J.
dc.contributor.authorRamírez Bellido, Alejandro
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-09-14T11:34:38Z
dc.date.available2017-09-14T11:34:38Z
dc.date.issued2003
dc.identifier.citationSantana, O., Ramírez , A., Valero, M. Latency tolerant branch predictors. A: International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems. "Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems". Maui, Hawaii: IEEE Press, 2003, p. 30-39.
dc.identifier.isbn0-7695-2019-7
dc.identifier.urihttp://hdl.handle.net/2117/107625
dc.description.abstractThe access latency of branch predictors is a well known problem of fetch engine design. Prediction overriding techniques are commonly accepted to overcome this problem. However, prediction overriding requires a complex recovery mechanism to discard the wrong speculative work based on overridden predictions. In this paper, we show that stream and trace predictors, which use long basic prediction units, can tolerate access latency without needing overriding, thus reducing fetch engine complexity. We show that both the stream fetch engine and the trace cache architecture not using overriding outperform other efficient fetch engines, such as an EV8-like fetch architecture or the FTB fetch engine, even when they do use overriding.
dc.format.extent10 p.
dc.language.isoeng
dc.publisherIEEE Press
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshCompilers (Computer programs)
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherParallel architectures
dc.subject.otherCache storage
dc.subject.otherSystem recovery
dc.subject.otherInstruction sets
dc.subject.otherProgram compilers
dc.titleLatency tolerant branch predictors
dc.typeConference report
dc.subject.lemacCompiladors (Programes d'ordinador)
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/IWIA.2003.1262780
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/1262780/
dc.rights.accessOpen Access
drac.iddocument21543190
dc.description.versionPostprint (published version)
upcommons.citation.authorSantana, O., Ramírez , A., Valero, M.
upcommons.citation.contributorInternational Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
upcommons.citation.pubplaceMaui, Hawaii
upcommons.citation.publishedtrue
upcommons.citation.publicationNameProceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems
upcommons.citation.startingPage30
upcommons.citation.endingPage39
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