Speculative dynamic vectorization
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Cita com:
hdl:2117/105265
Tipus de documentText en actes de congrés
Data publicació2002
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
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Abstract
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also present in irregular or pointer-rich codes, for which the compiler is quite limited to discover it. In this paper we propose a microarchitecture extension in order to exploit SIMD parallelism in a speculative way. The idea is to predict when certain operations are likely to be vectorizable, based on some previous history information. In this case, these scalar instructions are executed in a vector mode. These vector instructions operate on several elements (vector operands) that are anticipated to be their input operands and produce a number of outputs that are stored on a vector register in order to be used by further instructions. Verification of the correctness of the applied vectorization eventually changes the status of a given vector element from speculative to non-speculative, or alternatively, generates a recovery action in case of misspeculation. The proposed microarchitecture extension applied to a 4-way issue superscalar processor with one wide bus is 19% faster than the,same processor with 4 scalar buses to Ll data cache. This speed up is due basically to 1) the reduction in number of memory accesses, 15% for SpecInt and 20% for SpecFP, 2) the transformation of scalar arithmetic instructions into their vector counterpart, 28% for SpecInt and 23% for SpecFP, and 3) the exploitation of control independence for mispredicted branches.
CitacióPajuelo, M.A., González, A., Valero, M. Speculative dynamic vectorization. A: International Symposium on Computer Architecture. "29th Annual International Symposium on Computer Architecture: 25-29 May 2002, Anchorage, Alaska: proceedings". Anchorage, Alaska: Institute of Electrical and Electronics Engineers (IEEE), 2002, p. 271-280.
ISBN0-7695-1605-X
Versió de l'editorhttp://ieeexplore.ieee.org/abstract/document/1003585/
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