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This paper introduce a design review of a wideband Power Amplifier with a 65nm CMOS technology. The Integrated Circuit has to work from 300MHz to 2:5GHz with external
components adapted to a specific band. A 2.5D simulation of the QFN24 is lead to evaluate the parasitic effects generated
by the package. The one and two tones analysis are performed to characterize the PA. The 1dB Compression Point reach
10:36dBm and the Output referred Third order Interception Point is 23:98dBm. The Power Added Efficiency reached at the 1dB Compression Point is around 11:5% including the effect of the external components and the post-layout parasitics of the Integrated Circuit.
CitationDufis, C.; González, J. Design of a wideband class-A power amplifier for wireline communication. A: Conference on Design of Circuits and Integrated Systems. "XXV Conference on Design of Circuits and Integrated Systems". Lanzarote (Canaries): 2010, p. 339-344.
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