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Crossbar-based memristive logic-in-memory architecture
dc.contributor.author | Papandroulikadis, Georgios |
dc.contributor.author | Vourkas, Ioannis |
dc.contributor.author | Abustelema, Angel |
dc.contributor.author | Sirakoulis, Georgios |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2017-05-16T09:04:30Z |
dc.date.available | 2017-05-16T09:04:30Z |
dc.date.issued | 2017-04-01 |
dc.identifier.citation | Papandroulikadis, G., Vourkas, I., Abustelema, A., Sirakoulis, G., Rubio, A. Crossbar-based memristive logic-in-memory architecture. "IEEE transactions on nanotechnology", 1 Abril 2017, vol. 16, núm. 3, p. 491-501. |
dc.identifier.issn | 1536-125X |
dc.identifier.uri | http://hdl.handle.net/2117/104473 |
dc.description.abstract | The use of memristors and resistive random access memory (ReRAM) technology to perform logic computations, has drawn considerable attention from researchers in recent years. However, the topological aspects of the underlying ReRAM architecture and its organization have received less attention, as the focus has mainly been on device-specific properties for functionally complete logic gates through conditional switching in ReRAM circuits. A careful investigation and optimization of the target geometry is thus highly desirable for the implementation of logic-in-memory architectures. In this paper, we propose a crossbar-based in-memory parallel processing system in which, through the heterogeneity of the resistive cross-point devices, we achieve local information processing in a state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross-point selector devices. We primarily focus on the array organization, information storage, and processing flow, while proposing a novel geometry for the cross-point selection lines to mitigate current sneak-paths during an arbitrary number of possible parallel logic computations. We prove the proper functioning and potential capabilities of the proposed architecture through SPICE-level circuit simulations of half-adder and sum-of-products logic functions. We compare certain features of the proposed logic-in-memory approach with another work of the literature, and present an analysis of circuit resources, integration density, and logic computation parallelism. |
dc.format.extent | 11 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics |
dc.subject.lcsh | Memristors |
dc.subject.lcsh | Microelectromechanical systems |
dc.subject.lcsh | Electric switchgear |
dc.subject.lcsh | Nonvolatile random-access memory |
dc.subject.other | Computing |
dc.subject.other | Crossbar |
dc.subject.other | Digital logic |
dc.subject.other | Memristor |
dc.subject.other | |
dc.subject.other | Resistive RAM (ReRAM) |
dc.subject.other | Resistive switch |
dc.title | Crossbar-based memristive logic-in-memory architecture |
dc.type | Article |
dc.subject.lemac | Memòria d'accés aleatori |
dc.subject.lemac | Sistemes microelectromecànics |
dc.subject.lemac | Semiconductors de commutació |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.identifier.doi | 10.1109/TNANO.2017.2691713 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/7893787/ |
dc.rights.access | Open Access |
local.identifier.drac | 20566927 |
dc.description.version | Postprint (author's final draft) |
dc.relation.projectid | info:eu-repo/grantAgreement/MINECO//TEC2013-45638-C3-2-R/ES/APROXIMACION MULTINIVEL AL DISEÑO ORIENTADO A LA FIABILIDAD DE CIRCUITOS INTEGRADOS ANALOGICOS Y DIGITALES/ |
local.citation.author | Papandroulikadis, G.; Vourkas, I.; Abustelema, A.; Sirakoulis, G.; Rubio, A. |
local.citation.publicationName | IEEE transactions on nanotechnology |
local.citation.volume | 16 |
local.citation.number | 3 |
local.citation.startingPage | 491 |
local.citation.endingPage | 501 |
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