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dc.contributor.authorPapandroulikadis, Georgios
dc.contributor.authorVourkas, Ioannis
dc.contributor.authorAbustelema, Angel
dc.contributor.authorSirakoulis, Georgios
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2017-05-16T09:04:30Z
dc.date.available2017-05-16T09:04:30Z
dc.date.issued2017-04-01
dc.identifier.citationPapandroulikadis, G., Vourkas, I., Abustelema, A., Sirakoulis, G., Rubio, A. Crossbar-based memristive logic-in-memory architecture. "IEEE transactions on nanotechnology", 1 Abril 2017, vol. 16, núm. 3, p. 491-501.
dc.identifier.issn1536-125X
dc.identifier.urihttp://hdl.handle.net/2117/104473
dc.description.abstractThe use of memristors and resistive random access memory (ReRAM) technology to perform logic computations, has drawn considerable attention from researchers in recent years. However, the topological aspects of the underlying ReRAM architecture and its organization have received less attention, as the focus has mainly been on device-specific properties for functionally complete logic gates through conditional switching in ReRAM circuits. A careful investigation and optimization of the target geometry is thus highly desirable for the implementation of logic-in-memory architectures. In this paper, we propose a crossbar-based in-memory parallel processing system in which, through the heterogeneity of the resistive cross-point devices, we achieve local information processing in a state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross-point selector devices. We primarily focus on the array organization, information storage, and processing flow, while proposing a novel geometry for the cross-point selection lines to mitigate current sneak-paths during an arbitrary number of possible parallel logic computations. We prove the proper functioning and potential capabilities of the proposed architecture through SPICE-level circuit simulations of half-adder and sum-of-products logic functions. We compare certain features of the proposed logic-in-memory approach with another work of the literature, and present an analysis of circuit resources, integration density, and logic computation parallelism.
dc.format.extent11 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics
dc.subject.lcshMemristors
dc.subject.lcshMicroelectromechanical systems
dc.subject.lcshElectric switchgear
dc.subject.lcshNonvolatile random-access memory
dc.subject.otherComputing
dc.subject.otherCrossbar
dc.subject.otherDigital logic
dc.subject.otherMemristor
dc.subject.otherQQ
dc.subject.otherResistive RAM (ReRAM)
dc.subject.otherResistive switch
dc.titleCrossbar-based memristive logic-in-memory architecture
dc.typeArticle
dc.subject.lemacMemòria d'accés aleatori
dc.subject.lemacSistemes microelectromecànics
dc.subject.lemacSemiconductors de commutació
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/TNANO.2017.2691713
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/7893787/
dc.rights.accessOpen Access
local.identifier.drac20566927
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO//TEC2013-45638-C3-2-R/ES/APROXIMACION MULTINIVEL AL DISEÑO ORIENTADO A LA FIABILIDAD DE CIRCUITOS INTEGRADOS ANALOGICOS Y DIGITALES/
local.citation.authorPapandroulikadis, G.; Vourkas, I.; Abustelema, A.; Sirakoulis, G.; Rubio, A.
local.citation.publicationNameIEEE transactions on nanotechnology
local.citation.volume16
local.citation.number3
local.citation.startingPage491
local.citation.endingPage501


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