As semiconductor technology advances into the
nanoscale era, optical effects such as channel narrowing, corner
rounding or line-end pullback are critical to accomplish circuit
yield specifications. It is well-demonstrated that layout regularity
reduces the increasing impact of process variations on circuit
performance and reliability. The purpose of this paper is to
present the layout design of a regular cell based on 1-D elements
which reduces lithography perturbations (ALARC). We depict
several undesirable lithography effects and how these effects
determine several layout parameters in order to achieve the
required line-pattern resolution.
CitationGómez, S.; Moll, F. Lithography aware regular cell design based on a predictive technology model. A: European workshop on CMOS Variability. "The 1st European workshop on CMOS Variability". Montpellier: 2010.
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