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A large-scale spiking neural networks emulation architecture
dc.contributor | Madrenas Boadas, Jordi |
dc.contributor | Sánchez Rivera, Giovanny |
dc.contributor.author | Pirrone, Vito |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2014-10-13T12:30:34Z |
dc.date.available | 2014-10-13T12:30:34Z |
dc.date.issued | 2014-09-09 |
dc.identifier.uri | http://hdl.handle.net/2099.1/22996 |
dc.description.abstract | The purpose of this work is to design a new version (called SNAVA+) of the architecture SNAVA, an SNN hardware emulator implemented on a XilinX Kintex-7 FPGA. SNAVA+ increases the capabilities of SNAVA in order to have a large-scale SNN emulator. It preserves the basic hardware structure of SNAVA, making however several changes to optimize the performance. In particular, SNAVA+ project focuses on the aim to exploit more efficiently the availables resources, to reduce both the area and power consumption of the FPGA. A better use of the resources, in fact, is the main key to increase the potentiality of the SNN emulator, i.e. to increase the number of neurons and synapses simulated. |
dc.language.iso | eng |
dc.publisher | Universitat Politècnica de Catalunya |
dc.rights | S'autoritza la difusió de l'obra mitjançant la llicència Creative Commons o similar 'Reconeixement-NoComercial- SenseObraDerivada' |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació |
dc.subject.lcsh | Neural networks (Computer science) |
dc.subject.other | Spiking Neural Networks |
dc.subject.other | SNN hardware emulator |
dc.subject.other | hardware architecture |
dc.subject.other | FPGA |
dc.title | A large-scale spiking neural networks emulation architecture |
dc.type | Master thesis |
dc.subject.lemac | Xarxes neuronals (Informàtica) |
dc.identifier.slug | ETSETB-230.103992 |
dc.rights.access | Open Access |
dc.date.updated | 2014-10-10T05:51:52Z |
dc.audience.educationlevel | Màster |
dc.audience.mediator | Escola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona |
dc.audience.degree | MÀSTER UNIVERSITARI EN ENGINYERIA DE TELECOMUNICACIÓ (Pla 2013) |