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Improving The Robustness Of The Register File: a Register File Cache Architecture
| dc.contributor | Canal Corretger, Ramon |
| dc.contributor.author | Zhuang, Sicong |
| dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
| dc.date.accessioned | 2014-09-26T08:23:14Z |
| dc.date.available | 2014-09-26T08:23:14Z |
| dc.date.issued | 2014-09-09 |
| dc.identifier.uri | http://hdl.handle.net/2099.1/22656 |
| dc.description.abstract | This thesis exploits a multi-band cache-like register file architecture to mitigate the potential damage caused by process variations and soft error (single event upsets). An quantitative analysis is conducted to measure the possible gains and loses by incorporating it using simulation results. |
| dc.language.iso | eng |
| dc.publisher | Universitat Politècnica de Catalunya |
| dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| dc.subject.lcsh | Microprocessors |
| dc.subject.other | register file |
| dc.subject.other | process variation |
| dc.subject.other | soft error |
| dc.subject.other | register file |
| dc.subject.other | process variation |
| dc.subject.other | soft error |
| dc.title | Improving The Robustness Of The Register File: a Register File Cache Architecture |
| dc.type | Master thesis |
| dc.subject.lemac | Microprocessadors |
| dc.identifier.slug | 102852 |
| dc.rights.access | Open Access |
| dc.date.updated | 2014-09-12T04:00:16Z |
| dc.audience.educationlevel | Màster |
| dc.audience.mediator | Facultat d'Informàtica de Barcelona |
| dc.audience.degree | MÀSTER UNIVERSITARI EN INNOVACIÓ I RECERCA EN INFORMÀTICA (Pla 2012) |
