FPGA implementation of quadratic minimization algorithms for digital predistortion linearization
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The PA is one of the most important subsystems of the RF transmitter and it is responsible of the main part of the overall transmitter's power consumption. In order to increase the efficiency of the PA, this project proposes designing in a FPGA adaptive filtering techniques to update the coefficient of digital predistortion linearizers. More precisely, the least squares (LS) algorithm is design to be implemented in soft-core processor as the Xilinx MicroBlaze, while the least mean squares (LMS) algorithm is design for real-time operation in the FPGA. The experimental results obtained show a promising performance of the multi look-up table (M-LUT) based digital predistorter (DPD). Good linearity levels are reported. However, an exhaustive study on the required arithmetic resolution has yet to be carried out in order to mitigate the quantization noise and lead to a higher performance of the DPD using these kind of quadratic minimization algorithms.