English: Power consumption has become one of the dominant issues in processor
design, especially important in embedded systems and data
centers. One of possible solution that can address this issue and provide
higher performance for existing applications and new capabilities
for future applications used in hand-held devices and data centers is
to use vector processor.
This thesis presents the design and implementation of a vector library
that enables the vectorization of the target applications and allows to
We also present the ETModel: a simple trace-driven simulator for
vector processors. It is used to analyse the micro-architectural requirements
of the vectorized applications.
We show that the target applications are highly vectorizable with a
degree of vectorization from 62.9% for H264ref to 91% for ECLAT.
Detailed instruction level characteristics such as the distribution of
vector instructions, the distribution of vector lengths, etc. are also
presented in the thesis.
The thesis contains detailed timing analysis of the vectorized applications
for di erent micro-architectural con gurations of a vector processor.
We measured the execution time for the di erent con gurations
of cache hierarchy, main memory latencies, maximum vector
lengths and con guration of functional units, as well as the usage of
functional units. All these help in understanding the behavior of the
vectorized applications and requirements of vector micro-architecture.
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder. If you wish to make any use of the work not provided for in the law, please contact: firstname.lastname@example.org