Ponències/Comunicacions de congressos
http://hdl.handle.net/2117/3834
20150830T05:56:59Z

Coupled interleaved multicellular parallel converters operated under switching frequency modulation
http://hdl.handle.net/2117/26781
Coupled interleaved multicellular parallel converters operated under switching frequency modulation
Mon González, Juan; González Díez, David; Gautier, Cirylle; Labrousse, Denis; Costa, François
The Coupled Interleaved Multicellular Parallel (CIMP) topology is the subject of intense research
because of its advantages in terms of systems integration, power density increase, low level of EMI
emissions and dynamic performance. This paper evaluates the viability of application of switching
frequency modulation techniques to CIMP topology.
20140101T00:00:00Z

Improvement of driver to gate coupling circuits for SiC MOSFETS
http://hdl.handle.net/2117/26763
Improvement of driver to gate coupling circuits for SiC MOSFETS
Balcells Sendra, Josep; Mon González, Juan; Lamich Arocas, Manuel; Laguna, Alberto
This work presents a study of the influence of different gate driver circuits on the switching behavior of SiC MOSFET devices used in a buck converter. The paper is based on several tests performed to determine the switching times and switching losses, using different reverse bias VGS voltage levels and different passive RCD (Resistance Capacitor Diode) circuits to interface the driver to the SiC MOSFET gate.
20140101T00:00:00Z

A comparative study between Elliptic Fourier and Bspline descriptors for object contour representation
http://hdl.handle.net/2117/26572
A comparative study between Elliptic Fourier and Bspline descriptors for object contour representation
Ferrer Arnau, Luis Jorge; Parisi Baradad, Vicenç; Soria Pérez, José Antonio; Nasreddine, Kamal; Benzinou, Abdesslam
In this work, a comparative study between Elliptic
Fourier and Bspline descriptors is carried out for comparing
their efficiency in characterizing the contour shape of image
objects. In both cases, the goal is to obtain the least
representation error using the fewest possible number of
coefficients. With Fourier descriptors, different number of
harmonics are used while the remaining ones are set to zero. In
the Bspline case, coefficients are obtained iteratively using a
leastsquare filter, followed by a decimation procedure. Linear
and cubic Bsplines are considered. In general, data will be more
compressed when the lower number of coefficients is used, but
the representation error also increases considerably. We use a
signal/error ratio, expressed in dBs, to measure the similarity of
each approximation. The signal value is obtained from the
‘modulo’ addition of all coordinate points, whereas the error
value is computed accumulating the ‘modulo’ distance between
original and reconstructed shape. It can be shown that for a
lower compression rate, the results do not vary significantly in all
three methods. For higher compression rates, Elliptic Fourier
Descriptors are more efficient than linear and cubic Bsplines,
especially in soft contours, but Bsplines have lower
computational cost.
20140101T00:00:00Z

Modeling harmonics of networks supplying nonlinear loads
http://hdl.handle.net/2117/26314
Modeling harmonics of networks supplying nonlinear loads
Lamich Arocas, Manuel; Balcells Sendra, Josep; Corbalán Fuertes, Montserrat; Sainz Sapera, Luis; Fernandez, Cristian
This work presents the development and validation of a model for electric networks supplying nonlinear loads (NLL). The model is based on Neural Networks (NN) and its purpose is the prediction of harmonic currents sank by the loads, in case of supply impedance changes caused by the insertion or releasing of neighboring loads or by the voluntary insertion of filters to reduce such harmonic currents. The NN is trained using data obtained from several Matlab simulations and the model is validated using the same network with different supply impedances and load conditions.
20140101T00:00:00Z

Control to reduce leading current in a Shunt Hybrid power filter
http://hdl.handle.net/2117/26311
Control to reduce leading current in a Shunt Hybrid power filter
Lamich Arocas, Manuel; Balcells Sendra, Josep; González Díez, David; Gago Barrio, Javier; Jaen Fernandez, Carles; Castillo Martínez, José Luis
The main drawback of Shunt Hybrid Filters is the need of leading current injection. This paper describes a strategy
to reduce the leading current in a three phase four wires LC
coupled parallel hybrid filter for harmonics cancellation.
Simulation and experimental results are given to show the
behavior of the system.
20090101T00:00:00Z

Training kit for power electronics teaching
http://hdl.handle.net/2117/25871
Training kit for power electronics teaching
Pérez Robles, Daniel; Balcells Sendra, Josep; Lamich Arocas, Manuel; Berbel Artal, Néstor; Zaragoza Bertomeu, Jordi; Mon González, Juan
20080101T00:00:00Z

SiC modular multilevel converters: submodule voltage ripple analysis and efficiency estimations
http://hdl.handle.net/2117/24867
SiC modular multilevel converters: submodule voltage ripple analysis and efficiency estimations
Perez Basante, Angel; Pou Félix, Josep; Ceballos Recio, Salvador; Gil De Muro, Asier; Pujana, Ainhoa; Ibañez, Pedro
Two important technical challenges associated with the Modular Multilevel Converter (MMC) are the reduction of the voltage ripple of the SubModule (SM) capacitors and the reduction of the converter losses. This paper conducts a study focused on these two topics. Firstly, the effect of a circulating current with a predefined second harmonic on the SM voltage ripple is assessed. Secondly, an efficiency study for two different MMCs, one with silicon (Si) and the other with silicon carbide (SiC) devices is carried out. Results suggest that a SiC MMC converter with a circulating current including a second harmonic represent a good solution since it achieves a reduction of the SM capacitors together with a high efficiency operation.
20140101T00:00:00Z

Varying and unequal carrier frequency PWM techniques for modular multilevel converters
http://hdl.handle.net/2117/24865
Varying and unequal carrier frequency PWM techniques for modular multilevel converters
Konstantinou, Georgios; Darus, Rosheila; Pou Félix, Josep; Ceballos Recio, Salvador; Agelidis, Vassilios
Carrierbased pulsewidth modulation (PWM) strategies are commonly applied to modular multilevel converters (MMC). This paper proposes a modified PWM technique with unequal and varying carrier frequencies between consecutive levels. The variation between two consecutive carriers is calculated in order to maintain a constant average switching frequency regardless of modulation index and number of levels in the output. The proposed method effectively shifts the major harmonic content of output waveforms to higher frequencies at the cost of a slight increase in low order harmonics. Details on the derivation of the carrier frequencies as well as simulation and experimental results of the proposed method demonstrate the viability of the method as an alternative modulation technique for the MMC.
20140101T00:00:00Z

Comparison of phaseshifted and levelshifted PWM in the modular multilevel converter
http://hdl.handle.net/2117/24595
Comparison of phaseshifted and levelshifted PWM in the modular multilevel converter
Darus, Rosheila; Konstantinou, Georgios; Pou Félix, Josep; Ceballos Recio, Salvador; Agelidis, Vassilios
This paper reports a comparison study of different carrierbased PWM techniques applied to the modular multilevel converter. Phasedisposition PWM (PDPWM) and phaseshifted pulsewidth modulation (PSPWM) with noninterleaving and interleaving are considered in this study. In PSPWM, two cases are evaluated. In the first case, the particular SMs that have to be activated/deactivated are defined by a voltage balancing algorithm, which is the same one implemented in PDPWM. In addition, an algorithm to restrict the number of switching SMs is also implemented to reduce the switching frequency of the power devices. In the other case of PSPWM, each submodule (SM) has a carrier signal associated to it and capacitor voltage balance is achieved by individual control of its capacitor voltage. The circulating current is controlled to be a dc component in all the cases. Simulation and experimental results are presented to evaluate the quality of the linetoline output voltages and SM capacitor voltage ripples for the different cases under study. © 2014 IEEE.
20140101T00:00:00Z

A modified voltage balancing sorting algorithm for the modular multilevel converter: Evaluation for staircase and phasedisposition PWM
http://hdl.handle.net/2117/23161
A modified voltage balancing sorting algorithm for the modular multilevel converter: Evaluation for staircase and phasedisposition PWM
Darus, Rosheila; Pou Félix, Josep; Konstantinou, Georgios; Ceballos Recio, Salvador; Agelidis, Vassilios
This paper introduces a low complexity implementation of the voltage balancing sorting algorithm to reduce the switching frequency of the power devices in modular multilevel converters (MMCs). Two modulation techniques are evaluated; staircase modulation and phasedisposition pulsewidth modulation (PDPWM) under the conventional and the proposed algorithm. Using a circulating current controller in an MMC with 12 submodules per arm, PDPWM yields better results compared to the staircase modulation technique. The test condition for this comparison is such that the power devices operate at a similar switching frequency and produce similar amplitudes to the capacitor voltage ripples in both modulation techniques. The results are verified through extensive simulations and experimentally using a phaseleg MMC laboratory prototype.
20140101T00:00:00Z