Reports de recercahttp://hdl.handle.net/2117/6012024-03-28T19:22:59Z2024-03-28T19:22:59ZSemi-analytic discrete time model of a 1-stage CC-CPPalma Carmona, KennethMoll Echeto, Francisco de Borjahttp://hdl.handle.net/2117/3664622023-11-12T16:10:32Z2022-04-27T14:15:46ZSemi-analytic discrete time model of a 1-stage CC-CP
Palma Carmona, Kenneth; Moll Echeto, Francisco de Borja
This paper employs a linear, discrete-time State- Space model of a CMOS Cross-Coupled Charge Pump (CCCP.) The discrete-time model is based on the analytic solution of the differential equations at each semi-period. This model allows to determine the electrical parameters of the circuit without lengthy electrical simulations. The model is introduced and various simulations of the model are compared with the transient response of FDSOI implementations.
Poster - 2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS)
2022-04-27T14:15:46ZPalma Carmona, KennethMoll Echeto, Francisco de BorjaThis paper employs a linear, discrete-time State- Space model of a CMOS Cross-Coupled Charge Pump (CCCP.) The discrete-time model is based on the analytic solution of the differential equations at each semi-period. This model allows to determine the electrical parameters of the circuit without lengthy electrical simulations. The model is introduced and various simulations of the model are compared with the transient response of FDSOI implementations.Process variability in sub-16nm bulk CMOS technologyRubio Sola, Jose AntonioFigueras Pàmies, JoanVatajelu, Elena IoanaCanal Corretger, Ramonhttp://hdl.handle.net/2117/156672020-07-23T22:19:06Z2012-03-26T18:45:53ZProcess variability in sub-16nm bulk CMOS technology
Rubio Sola, Jose Antonio; Figueras Pàmies, Joan; Vatajelu, Elena Ioana; Canal Corretger, Ramon
The document is part of deliverable D3.6 of the TRAMS Project (EU FP7 248789), of public nature, and shows and justifies the levels of variability used in the research project for sub-18nm bulk CMOS technologies.
2012-03-26T18:45:53ZRubio Sola, Jose AntonioFigueras Pàmies, JoanVatajelu, Elena IoanaCanal Corretger, RamonThe document is part of deliverable D3.6 of the TRAMS Project (EU FP7 248789), of public nature, and shows and justifies the levels of variability used in the research project for sub-18nm bulk CMOS technologies.Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitorsGanapathy, ShrikanthCanal Corretger, RamonGonzález Colás, Antonio MaríaRubio Sola, Jose Antoniohttp://hdl.handle.net/2117/150192020-07-23T22:56:18Z2012-02-08T12:50:44ZDynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors
Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio
In this paper, we propose a dynamically tunable fine-grain body biasing mechanism to reduce active & standby leakage power in caches under process variations.
2012-02-08T12:50:44ZGanapathy, ShrikanthCanal Corretger, RamonGonzález Colás, Antonio MaríaRubio Sola, Jose AntonioIn this paper, we propose a dynamically tunable fine-grain body biasing mechanism to reduce active & standby leakage power in caches under process variations.On the effectiveness of hybrid mechanisms on reduction of parametric failures in cachesGanapathy, ShrikanthCanal Corretger, RamonGonzález Colás, Antonio MaríaRubio Sola, Jose Antoniohttp://hdl.handle.net/2117/150072020-07-23T22:12:52Z2012-02-08T11:07:29ZOn the effectiveness of hybrid mechanisms on reduction of parametric failures in caches
Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio
In this paper, we provide an insight on the different proactive read/write assist methods (wordline boosting & adaptive body biasing) that help in preventing (and reducing) parametric failures when coupled with reactive techniques like ECC and redundancy which cope with already existent failures. While proactive and reactive have been previously viewed as complementary techniques, we show that it is not necessarily the case when considering the benefits of such hybrid schemes.
2012-02-08T11:07:29ZGanapathy, ShrikanthCanal Corretger, RamonGonzález Colás, Antonio MaríaRubio Sola, Jose AntonioIn this paper, we provide an insight on the different proactive read/write assist methods (wordline boosting & adaptive body biasing) that help in preventing (and reducing) parametric failures when coupled with reactive techniques like ECC and redundancy which cope with already existent failures. While proactive and reactive have been previously viewed as complementary techniques, we show that it is not necessarily the case when considering the benefits of such hybrid schemes.vPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cellsGanapathy, ShrikanthCanal Corretger, RamonGonzález Colás, Antonio MaríaRubio Sola, Jose Antoniohttp://hdl.handle.net/2117/139112020-07-22T17:57:10Z2011-11-15T14:28:57ZvPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cells
Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio
In this paper, we present an on-die post-silicon binning methodology that takes into account the effect of static and dynamic variations and categorizes every processor based on power/performance.The proposed scheme is composed of a discretization hardware that exploits the delay/leakage dependence on variability sources characteristic for categorization
2011-11-15T14:28:57ZGanapathy, ShrikanthCanal Corretger, RamonGonzález Colás, Antonio MaríaRubio Sola, Jose AntonioIn this paper, we present an on-die post-silicon binning methodology that takes into account the effect of static and dynamic variations and categorizes every processor based on power/performance.The proposed scheme is composed of a discretization hardware that exploits the delay/leakage dependence on variability sources characteristic for categorizationFOCSI: A new layout regularity metricPons Solé, MarcMoll Echeto, Francisco de BorjaRubio Sola, Jose AntonioAbella Ferrer, JaumeVera Rivera, Francisco JavierGonzález Colás, Antonio Maríahttp://hdl.handle.net/2117/133852020-07-22T17:33:08Z2011-09-29T08:11:25ZFOCSI: A new layout regularity metric
Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María
Digital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce these ICs systematic subwavelength lithography failures. However, there is no metric to evaluate and compare the layout regularity of those regular designs.
In this paper we propose a new layout regularity metric
called Fixed Origin Corner Square Inspection (FOCSI).
FOCSI allows the comparison and quantification of designs
in terms of regularity and for any given degree of
granularity. When FOCSI is oriented to the evaluation
of regularity while applying Lithography Enhancement
Techniques, it comprehends layout layers measurements
considering the optical interaction length
and combines them to obtain the complete layout regularity
measure. Examples are provided for 32-bit adders
in the 90 nm technology node for the Standard Cell approach
and for Via-Configurable Transistor Array regular
designs. We show how layouts can be sorted accurately
even if their degree of regularity is similar.
Technical Report
2011-09-29T08:11:25ZPons Solé, MarcMoll Echeto, Francisco de BorjaRubio Sola, Jose AntonioAbella Ferrer, JaumeVera Rivera, Francisco JavierGonzález Colás, Antonio MaríaDigital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce these ICs systematic subwavelength lithography failures. However, there is no metric to evaluate and compare the layout regularity of those regular designs.
In this paper we propose a new layout regularity metric
called Fixed Origin Corner Square Inspection (FOCSI).
FOCSI allows the comparison and quantification of designs
in terms of regularity and for any given degree of
granularity. When FOCSI is oriented to the evaluation
of regularity while applying Lithography Enhancement
Techniques, it comprehends layout layers measurements
considering the optical interaction length
and combines them to obtain the complete layout regularity
measure. Examples are provided for 32-bit adders
in the 90 nm technology node for the Standard Cell approach
and for Via-Configurable Transistor Array regular
designs. We show how layouts can be sorted accurately
even if their degree of regularity is similar.THERMAL OBSERVATION OF A MODULATED INPUT FOR A 2.5GHZ CMOS POWER AMPLIFIER Part 3: PA+Sensor layout integration and PVT analysisMartín, MikelGonzález Jiménez, José Luishttp://hdl.handle.net/2117/130552020-07-23T23:27:30Z2011-07-26T17:38:37ZTHERMAL OBSERVATION OF A MODULATED INPUT FOR A 2.5GHZ CMOS POWER AMPLIFIER Part 3: PA+Sensor layout integration and PVT analysis
Martín, Mikel; González Jiménez, José Luis
The objective is to detect the impact of PVT variations (Process, Voltage and Temperature variations) on the figures of merit of a device.
2011-07-26T17:38:37ZMartín, MikelGonzález Jiménez, José LuisThe objective is to detect the impact of PVT variations (Process, Voltage and Temperature variations) on the figures of merit of a device.THERMAL OBSERVATION OF A MODULATED INPUT FOR A 2.5GHZ CMOS POWER AMPLIFIER Part 2: Temperature SensorMartín, MikelGonzález Jiménez, José Luishttp://hdl.handle.net/2117/130542020-07-23T22:27:24Z2011-07-26T17:36:51ZTHERMAL OBSERVATION OF A MODULATED INPUT FOR A 2.5GHZ CMOS POWER AMPLIFIER Part 2: Temperature Sensor
Martín, Mikel; González Jiménez, José Luis
The temperature sensor used is based on the usual two bipolar transistors temperature sensor with some modifications to allow for external calibration (or “re-centering”).
2011-07-26T17:36:51ZMartín, MikelGonzález Jiménez, José LuisThe temperature sensor used is based on the usual two bipolar transistors temperature sensor with some modifications to allow for external calibration (or “re-centering”).THERMAL OBSERVATION OF A MODULATED INPUT FOR A 2.5GHZ CMOS POWER AMPLIFIER Part 1: Feasibility studyMartin, MikelGonzález Jiménez, José Luishttp://hdl.handle.net/2117/130532020-07-23T21:03:21Z2011-07-26T17:33:53ZTHERMAL OBSERVATION OF A MODULATED INPUT FOR A 2.5GHZ CMOS POWER AMPLIFIER Part 1: Feasibility study
Martin, Mikel; González Jiménez, José Luis
In this Project, the verification of the possibility of extraction of information of a modulated signal through no-invasive thermal measurements is done. The main objective is that using a non-invasive thermal technique, information about the PA can be extracted so that the PA’s efficiency can be improved.
2011-07-26T17:33:53ZMartin, MikelGonzález Jiménez, José LuisIn this Project, the verification of the possibility of extraction of information of a modulated signal through no-invasive thermal measurements is done. The main objective is that using a non-invasive thermal technique, information about the PA can be extracted so that the PA’s efficiency can be improved.CATRENE-PANAMA project review November 2010González Jiménez, José LuisDufis, Cédric Yvanhttp://hdl.handle.net/2117/121392020-07-22T17:46:02Z2011-03-29T12:50:52ZCATRENE-PANAMA project review November 2010
González Jiménez, José Luis; Dufis, Cédric Yvan
Informe de progrés del projecte Europeu CATRENE-PANAMA sobre les tasques desenvolupades per el grup de recerca HiPICS de la UPC
2011-03-29T12:50:52ZGonzález Jiménez, José LuisDufis, Cédric YvanInforme de progrés del projecte Europeu CATRENE-PANAMA sobre les tasques desenvolupades per el grup de recerca HiPICS de la UPC