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| Boosting single-thread.pdf | | 651 kB | Adobe PDF |  |
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| Citació: | Madriles, C. [et al.]. Boosting single-thread performance in multi-core systems through fine-grain multi-threading. A: International Symposium on Computer Architecture. "International Symposium on Computer Architecture". Austin, TX: ACM Press. Association for Computing Machinery, 2009, p. 474-483. |
| Títol: | Boosting single-thread performance in multi-core systems through fine-grain multi-threading |
| Autor: | Madriles Gimeno, Carles; López Muñoz, Pedro; Codina, Josep Maria; Gibert Codina, Enric ; Latorre Salinas, Fernando ; Martínez Vicente, Alejandro ; Martinez Morais, Raul; González Colás, Antonio María  |
| Editorial: | ACM Press. Association for Computing Machinery |
| Data: | jun-2009 |
| Tipus de document: | Conference report |
| Resum: | Industry has shifted towards multi-core designs as we have hit the memory and power walls. However, single thread performance
remains of paramount importance since some applications have limited thread-level parallelism (TLP), and even a small part with
limited TLP impose important constraints to the global performance, as explained by Amdahl’s law.
In this paper we propose a novel approach for leveraging multiple cores to improve single-thread performance in a multi-core
design. The proposed technique features a set of novel hardware mechanisms that support the execution of threads generated at
compile time. These threads result from a fine-grain speculative decomposition of the original application and they are executed
under a modified multi-core system that includes: (1) mechanisms to support multiple versions; (2) mechanisms to detect violations
among threads; (3) mechanisms to reconstruct the original sequential order; and (4) mechanisms to checkpoint the architectural state and recovery to handle misspeculations.
The proposed scheme outperforms previous hardware-only schemes to implement the idea of combining cores for executing
single-thread applications in a multi-core design by more than 10% on average on Spec2006 for all configurations. Moreover,
single-thread performance is improved by 41% on average when the proposed scheme is used on a Tiny Core, and up to 2.6x for some selected applications. |
| ISBN: | 978-1-60558-526-0 |
| URI: | http://hdl.handle.net/2117/7925 |
| Versió de l'editor: | http://doi.acm.org/10.1145/1555754.1555813 |
| Apareix a les col·leccions: | Altres. Enviament des de DRAC Departament d'Arquitectura de Computadors. Ponències/Comunicacions de congressos ARCO - Microarquitectura i Compiladors. Ponències/Comunicacions de congressos
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