Acceleration of Complex Algorithms on a Fast Reconfigurable Embedded System on Spartan-3
Visualitza/Obre
Tipus de documentText en actes de congrés
Data publicació2009
Condicions d'accésAccés obert
Llevat que s'hi indiqui el contrari, els
continguts d'aquesta obra estan subjectes a la llicència de Creative Commons
:
Reconeixement-NoComercial-SenseObraDerivada 3.0 Espanya
Abstract
Complex algorithms usually require several computation
stages. Many embedded microprocessors have not enough
computational performance to resolve these algorithms in a
reasonable time, so dedicated coprocessors accelerate them
although the main drawback is the area devoted to them. A
reconfigurable coprocessor can drastically reduce the area,
since it accommodates a set of coprocessors whose
execution is multiplexed on time, although the
reconfiguration speed reduces the overall system
performance. Although self-reconfigurable systems are
possible on Spartan-3 FPGAs, it requires a hard design
task due to the lack of software and hardware support
available on higher-cost families. This paper describes the
architecture of a fast self-reconfigurable embedded system
mapped on Spartan-3, used as computation platform to
solve a complex algorithm, such as the image-processing
carried out in a fingerprint biometric algorithm. In order to
reduce the reconfiguration time, the system uses our
custom-made memory and reconfiguration controllers.
Moreover, the dynamic coprocessor can access directly to
external memory through our memory controller to
improve processing time.
CitacióCanto, E. [et al.]. Acceleration of Complex Algorithms on a Fast Reconfigurable Embedded System on Spartan-3. A: International Conference on Field Programmable Logic and Applications. "19th International Conference on Field Programmable Logic and Applications". Prague: 2009, p. 429-434.
ISBN978-1-4244-3892-1
Versió de l'editorhttp://fpl2009.org/
Fitxers | Descripció | Mida | Format | Visualitza |
---|---|---|---|---|
W2B_2.pdf | 815,8Kb | Visualitza/Obre |