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HIPICS - High Performance Integrated Circuits and Systems

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Vista preliminarDataTítolAutor(s)
Variability_Scenarios.pdf.jpg1-mar-2012Process variability in sub-16nm bulk CMOS technologyRubio Sola, Jose Antonio; Figueras Pàmies, Joan; Vatajelu, Elena Ioana; Canal Corretger, Ramon
5-des-2011On the effectiveness of hybrid mechanisms on reduction of parametric failures in cachesGanapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio
16-mai-2011THERMAL OBSERVATION OF A MODULATED INPUT FOR A 2.5GHZ CMOS POWER AMPLIFIER Part 3: PA+Sensor layout integration and PVT analysisMartín, Mikel; González Jiménez, José Luis
25-abr-2011THERMAL OBSERVATION OF A MODULATED INPUT FOR A 2.5GHZ CMOS POWER AMPLIFIER Part 2: Temperature SensorMartín, Mikel; González Jiménez, José Luis
Dynamic fine-grain body biasing ....pdf.jpg15-abr-2011Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitorsGanapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio
16-mar-2011Inforrme de la segona anualitat del projecte CATRENE-PANAMA per al programa AVANZA I+DGonzález Jiménez, José Luis; Dufis, Cédric Yvan
2-mar-2011THERMAL OBSERVATION OF A MODULATED INPUT FOR A 2.5GHZ CMOS POWER AMPLIFIER Part 1: Feasibility studyMartin, Mikel; González Jiménez, José Luis
23-nov-2010CATRENE-PANAMA project review November 2010González Jiménez, José Luis; Dufis, Cédric Yvan
ganapathy_date_2011_submitted.pdf.jpg5-set-2010vPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cellsGanapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio
3-jun-2010CATRENE-PANAMA project review June 2010González Jiménez, José Luis; Dufis, Cédric Yvan
WP1_M1_3_Report.pdf.jpg30-oct-2009CATRENE-PANAMA WP1: integrated PA Milestone M1.3 technology, approach & system choice for home networkingDufis, Cédric Yvan; Mateo Peña, Diego; Bofill, Adrià; González Jiménez, José Luis
FOCSI.pdf.jpg9-jun-2009FOCSI: A new layout regularity metricPons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María
AssuraRCX_HF_AMS.pdf.jpg31-oct-2008Set-up of Assura RCX-HF tools for the AMS S35 process. Configuration files and usage guide.Aragonès Cervera, Xavier
TRDDOCT-06-0001.pdf.jpgjun-2006Energy macro-model for on chip interconnection busesMendoza Vázquez, Raymundo; Pons Solé, Marc; Moll Echeto, Francisco de Borja; Figueras, Joan

 

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