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| Vista preliminar | Data | Títol | Autor(s) |  | 1-mar-2012 | Process variability in sub-16nm bulk CMOS technology | Rubio Sola, Jose Antonio; Figueras Pàmies, Joan; Vatajelu, Elena Ioana; Canal Corretger, Ramon |
| 5-des-2011 | On the effectiveness of hybrid mechanisms on reduction of parametric failures in caches | Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio |
 | 19-set-2011 | A selective logging mechanism for hardware transactional memory systems | Lupon Navazo, Marc; Magklis, Grigorios; González Colás, Antonio María |
 | 15-abr-2011 | Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors | Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio |
 | 5-set-2010 | vPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cells | Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio |
 | 27-ago-2010 | Implementing a hybrid SRAM / eDRAM NUCA architecture | Lira Rueda, Javier; Molina Clemente, Carlos; Brooks, David; González Colás, Antonio María |
 | 9-jun-2009 | FOCSI: A new layout regularity metric | Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María |
 | 14-mai-2009 | LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors | Lira Rueda, Javier; Molina Clemente, Carlos; González Colás, Antonio María |
 | 16-gen-2009 | Last Bank: dealing with address reuse in non-uniform cache architecture for CMPs | Lira Rueda, Javier; Molina Clemente, Carlos; González Colás, Antonio María |
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