Look-up table implementation of a slow envelope dependent digital predistorter for envelope tracking power amplifiers

Abstract

This letter presents a dynamic slow envelope dependent digital predistorter (SED-DPD) capable of compensating for the nonlinear distortion and memory effects that arise in envelope tracking (ET) power amplifiers (PAs) when using a slow version of the signal's envelope to dynamically supply the PA drain voltage. Moreover, a new DPD architecture based on the combination of several basic predistortion cells (BPCs) is presented to allow the FPGA implementation of the proposed SED-DPD. Finally, results showing the necessity and linearization performance of the proposed dynamic SED-DPD are provided.