Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy

Abstract

One of the main objectives of the data computing and memory industry is to keep and ever accelerate the increase of component density reached in nowadays integrated circuits in future technologies based on ultimate CMOS and new emerging research devices. The worldwide-accepted predictions with these technologies indicate a remarkable reduction of the components quality, because of the manufacturing process complexity and the erratic behavior of devices, causing a drop in the system reliability if we maintain the same design rules than today. Together with the introduction of new devices, new architectural design paradigms have to be included. Fault tolerant techniques are considered necessary and relevant in this scenario. In this paper we present a Fault-Tolerant Nanoscale architecture based on the implementation of logic systems with averaging cells linear threshold gates (AC-LTG). The sensitivity of the gates in relation with manufacturing and environment deviation is investigated and compared with the well known NAND multiplexing concept, showing that the AC-LTG is a valuable alternative in specific nanoscale conditions.