DSpace DSpace UPC
 Català   Castellano   English  

E-prints UPC >
Altres >
Enviament des de DRAC >

Empreu aquest identificador per citar o enllaçar aquest ítem: http://hdl.handle.net/2117/15657

Ítem no disponible en accés obert per política de l'editorial

Arxiu Descripció MidaFormat
Alarcon_IEEE Transact _An Ultra_05929555.pdf1,64 MBAdobe PDF Accés restringit

Citació: Rodriguez, J. [et al.]. An ultra low-power mixed-signal back-end for passive sensor UHF RFID transponders. "IEEE transactions on industrial electronics", Febrer 2012, vol. 59, núm. 2, p. 1310-1322.
Títol: An ultra low-power mixed-signal back-end for passive sensor UHF RFID transponders
Autor: Rodriguez, J.; Delgado Restituto, M.; Masuch, J.; Rodriguez Perez, Alberto; Alarcón Cot, Eduardo José Veure Producció científica UPC; Rodríguez Vázquez, Ángel
Editorial: IEEE Press. Institute of Electrical and Electronics Engineers
Data: feb-2012
Tipus de document: Article
Resum: This paper describes the design of mixed-signal back end for an ultrahigh-frequency sensor-enabled radio-frequency identification transponder in full compliance with the Electronic Product Code Class-1 Generation-2 protocol, defined in the standard ISO 18000-6C. The chip, implemented in a low-cost 0.35- μm CMOS technology process, includes a baseband processor, an analog-to-digital converter (ADC) to digitize the signal acquired from the external sensor, and some auxiliary circuitry for voltage regulation and reference generation. The proposed solution uses two different supply voltages, one for the processor and the other for the mixed-signal circuitry, and defines a novel communication protocol between both blocks so that analog readouts are minimally affected by the digital activity of the tag. The whole system was first functionally validated by exhaustively testing with external dc power supplies ten prototype samples, and then, the two main blocks, processor, and ADC were individually tested to assess their performance limits. Regarding the baseband processor, experiments were performed toward the calculation of its packet error rate (PER) under two typical biasing configurations of passive tags, using either crude clamps or regulators. It was found that the regulated biasing outperforms the clamping solution and obtains a PER of 3 × 10-3 with a supply voltage of 0.75 V. The current consumption of the processor during the reception and response to a Read command at maximum backward rate is only 2.2 μA from a 0.9-V supply. Regarding the ADC, it is a 10-b successive approximation register converter which obtains 9.41 b of effective resolution at 2-kS/s sampling frequency with a power consumption of 250 nW, including the dissipation of a current generation cell and the clock generation circuitry, from 1-V supply.
ISSN: 0278-0046
URI: http://hdl.handle.net/2117/15657
DOI: 10.1109/TIE.2011.2159695
Versió de l'editor: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5929555
Apareix a les col·leccions:Altres. Enviament des de DRAC
EPIC - Disseny de circuits analògics integrats i de convertidors de potencia conmutats. Articles de revista
Departament d'Enginyeria Electrònica. Articles de revista
Comparteix:


Stats Mostra les estadístiques d'aquest ítem

SFX Query

Tots els drets reservats. Aquesta obra està protegida pels drets de propietat intel·lectual i industrial corresponents. Sense perjudici de les exempcions legals existents, queda prohibida la seva reproducció, distribució, comunicació pública o transformació sense l'autorització del titular dels drets.

Per a qualsevol ús que se'n vulgui fer no previst a la llei, dirigiu-vos a: sepi.bupc@upc.edu

 

Valid XHTML 1.0! Programari DSpace Copyright © 2002-2004 MIT and Hewlett-Packard Comentaris
Universitat Politècnica de Catalunya. Servei de Biblioteques, Publicacions i Arxius