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| Citació: | Bhagat, I. [et al.]. Global productiveness propagation: A code optimization technique to speculatively prune useless narrow computations. A: ACM SIGPLAN/SIGBED Conference on Languages Compilers, Tools, and Theory for Embedded Systems. "2011 ACM SIGPLAN/SIGBED Conference on Languages Compilers, Tools, and Theory for Embedded Systems". ACM Press, NY, 2011, p. 161-170. |
| Títol: | Global productiveness propagation: A code optimization technique to speculatively prune useless narrow computations |
| Autor: | Bhagat, Indu ; Gibert Codina, Enric ; Sanchez, Jesus; González Colás, Antonio María  |
| Editorial: | ACM Press, NY |
| Data: | 2011 |
| Tipus de document: | Conference report |
| Resum: | This paper proposes a unique hardware-software collaborative strategy to remove useless work at 16-bit data-width granularity. The underlying motivation is to design a low power execution platform by exploiting ‘narrow’ computations. The proposal uses a strictly narrow bit-wide microarchitecture (16-bit integer datapath),
which realizes the goal of a low cost, low hardware complexity, low power execution engine. Software dynamically maps the 64-bit computations by translating them into an equivalent 16-bit instruction stream and optimizing them.
In this paper, we propose an optimization technique, called Global Productiveness Propagation (GPP), which is a dynamic,
profile-based optimization technique that infers the minimum required dataflow by pruning narrow computations that are mostprobably useless (non-productive). More precisely, GPP speculatively prunes the static backward slices of selected narrow computations: computations that result in the same value (in their respective storage location) as that at the input of the region. This speculative optimization technique is formulated around the concept
of ‘narrow’ computations because the same allow a finer granularity to distinguish between useful (productive) and useless (nonproductive) work. GPP has been evaluated on an in-order narrow bit-wide execution core, achieving an average dynamic instruction stream reduction of 6.6%, while improving overall performance by 4.2%. |
| URI: | http://hdl.handle.net/2117/13872 |
| Apareix a les col·leccions: | Altres. Enviament des de DRAC Departament d'Arquitectura de Computadors. Ponències/Comunicacions de congressos ARCO - Microarquitectura i Compiladors. Ponències/Comunicacions de congressos
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