Lithography aware regular cell design based on a predictive technology model

Abstract

As semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated that layout regularity reduces the increasing impact of process variations on circuit performance and reliability. The aim of this paper is to present the layout design of a regular cell based on 1-D elements which reduces lithography perturbations (ALARC). We depict several undesirable lithography effects and how these distortions determine several layout parameters in order to achieve the required line-pattern resolution. Furthermore, it is shown how the measurement of leakage power consumption based on ideal layout is not a precise metric to evaluate circuit performance, especially for low power designs. Finally, the impact of lithography patterns on delay and leakage consumption of a typical cell is provided.