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Citació: Beltran, V. [et al.]. CellMT: A cooperative multithreading library for the Cell/B.E.. A: International Conference on High Performance Computing. "16th International Conference on High Performance Computing". Kochi: IEEE Computer Society Publications, 2009, p. 245-253.
Títol: CellMT: A cooperative multithreading library for the Cell/B.E.
Autor: Beltran Querol, Vicenç; Carrera Pérez, David Veure Producció científica UPC; Torres Viñals, Jordi Veure Producció científica UPC; Ayguadé Parra, Eduard Veure Producció científica UPC
Editorial: IEEE Computer Society Publications
Data: 16-des-2009
Tipus de document: Conference report
Resum: The Cell BE processor has proved that heterogeneous multi-core systems can provide a huge computational power with high efficiency for a wide range of applications. The simple design of the computational units and the use of small managed local memories is the key to achieve high efficiency and performance at the same time. However, this simple and efficient hardware design comes at the price of higher code complexity. The code written to run in this kind of processors must deal with several issues such as code vectorization, loop unrolling or the explicit management of local memories. Some of these issues such as vectorization or loop unrolling can be partially solved by the compiler, but the overlapping of data transfer and computation times must be manually addressed by the programmer with techniques such as double buffering that increase the code complexity. In this paper we present a user level threading library called CellMT that effectively hide memory latencies. The concurrent execution of several threads inside each SPU naturally overlaps computation and data transfer times without increasing the code complexity. To prove the suitability and feasibility of our multi-threaded library, we perform an exhaustive performance evaluation with a synthetic benchmark and a real application. The experimental results show that the multithreaded approach can outperform a hand-coded double buffering scheme, with speedups from 0.96x to 3.2x, while maintaining the complexity of a naive buffering scheme.
URI: http://hdl.handle.net/2117/10016
DOI: 10.1109/HIPC.2009.5433205
Apareix a les col·leccions:CAP - Grup de Computació d´Altes Prestacions. Ponències/Comunicacions de congressos
Departament d'Arquitectura de Computadors. Ponències/Comunicacions de congressos
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