http://hdl.handle.net/2117/3938 Fri, 24 May 2013 09:25:22 GMT 2013-05-24T09:25:22Z webmaster.bupc@upc.edu Universitat Politècnica de Catalunya. Servei de Biblioteques i Documentació no http://hdl.handle.net/2117/19372 Title: Implementation of the Direct Torque Control (DTC) in current model, with current starting limiter Authors: Mino Aguilar, Gerardo; Muñoz Hernández, German Ardul; Romeral Martínez, José Luis; Cortez, Liliana; Saynes Torres, J. Abstract: This paper presents the scheme of Direct Torque Control (DTC) for induction motor drives, where flux and torque of the motor are estimated by the IM current model. Its scheme requires the knowledge of speed, rotor time constant and inductive parameters of the motor. The results prove the excellent characteristics for torque response and efficiency, which confirm the validity of this control scheme. Due to the rapid response offered by the DTC, this causes a high star current inversor protections activating. To resolve this, is presents the implementation of a closed loop of current vector the optimum switching table that limits the current and put into operation to the DTC. Experimental tests demonstrate effectiveness. Wed, 22 May 2013 11:30:26 GMT http://hdl.handle.net/2117/19372 2013-05-22T11:30:26Z Mino Aguilar, Gerardo; Muñoz Hernández, German Ardul; Romeral Martínez, José Luis; Cortez, Liliana; Saynes Torres, J. no current limiter, current model, DTC This paper presents the scheme of Direct Torque Control (DTC) for induction motor drives, where flux and torque of the motor are estimated by the IM current model. Its scheme requires the knowledge of speed, rotor time constant and inductive parameters of the motor. The results prove the excellent characteristics for torque response and efficiency, which confirm the validity of this control scheme. Due to the rapid response offered by the DTC, this causes a high star current inversor protections activating. To resolve this, is presents the implementation of a closed loop of current vector the optimum switching table that limits the current and put into operation to the DTC. Experimental tests demonstrate effectiveness. http://hdl.handle.net/2117/19339 Title: Mathematical model of total cross-tied photovoltaic arrays in mismatching conditions Authors: Ramos Paja, Carlos Andres; Bastidas, Juan David; Saavedra Montes, Andres Julian; Guinjoan Gispert, Francisco; Goez, M. Abstract: This paper presents a mathematical procedure for modeling rectangular (N rows with M modules each) and non-rectangular photovoltaic (PV) arrays in Total Cross-Tied (TCT) configuration operating in uniform and mismatching conditions. The proposed model uses the simple single diode representation for each PV module; then each row of the TCT array is represented as an equivalent non-linear PV circuit with a bypass diode, which allows to represent the TCT array as one string of equivalent PV circuits. The inflection voltages (array voltages that turn off the bypass diodes) of the string are calculated in order to solve only the non-linear equation system related to the active equivalent PV circuits for calculating the array current for a given voltage. Such a strategy reduces the computational burden and improves calculation speed. A TCT array of 4×2 with deep mismatching conditions was implemented in PSIM software to validate the proposed model, obtaining a correlation between model predicted data and the circuital simulation. The accuracy and improved calculation speed of the proposed model allow its use altogether with reconfiguration techniques as well as to reduce the time of energetic evaluations of TCT arrays for PV planning. Fri, 17 May 2013 13:38:51 GMT http://hdl.handle.net/2117/19339 2013-05-17T13:38:51Z Ramos Paja, Carlos Andres; Bastidas, Juan David; Saavedra Montes, Andres Julian; Guinjoan Gispert, Francisco; Goez, M. no Array voltage, Bypass diodes, Calculation speed, Computational burden, Mathematical procedures, Nonlinear equation system, Photovoltaic arrays, PV modules This paper presents a mathematical procedure for modeling rectangular (N rows with M modules each) and non-rectangular photovoltaic (PV) arrays in Total Cross-Tied (TCT) configuration operating in uniform and mismatching conditions. The proposed model uses the simple single diode representation for each PV module; then each row of the TCT array is represented as an equivalent non-linear PV circuit with a bypass diode, which allows to represent the TCT array as one string of equivalent PV circuits. The inflection voltages (array voltages that turn off the bypass diodes) of the string are calculated in order to solve only the non-linear equation system related to the active equivalent PV circuits for calculating the array current for a given voltage. Such a strategy reduces the computational burden and improves calculation speed. A TCT array of 4×2 with deep mismatching conditions was implemented in PSIM software to validate the proposed model, obtaining a correlation between model predicted data and the circuital simulation. The accuracy and improved calculation speed of the proposed model allow its use altogether with reconfiguration techniques as well as to reduce the time of energetic evaluations of TCT arrays for PV planning. http://hdl.handle.net/2117/19338 Title: Resonant pulse-shaping power supply for radar transmitters Authors: Bell Rodriguez, Miguel Victoria Ramo; Roberg, Michael; Pack, Riley; Garcia Fernandez, Pablo; Alarcón Cot, Eduardo José; Popoviç, Zoya; Maksimovic, Dragan Abstract: The final radiofrequency power amplifier (PA) of a radar transmitter module is a large factor in system efficiency. Typical radar transmitter signals are frequency-modulated with constant-amplitude pulse envelopes in order to optimize efficiency, resulting in spectral broadening and power radiated outside of the radar frequency band. This paper demonstrates a PA with a dynamic power supply which enables high efficiency while reducing the spectral emissions. The resonant pulse-shaping power supply generates a raised-cosine pulse envelope waveform with efficiency greater than 90% and peak envelope power around 6 W. Measured results with a 2.14-GHz GaN power amplifier with an efficiency of 76% at peak power demonstrate over 67% transmitter efficiency. Fri, 17 May 2013 13:29:14 GMT http://hdl.handle.net/2117/19338 2013-05-17T13:29:14Z Bell Rodriguez, Miguel Victoria Ramo; Roberg, Michael; Pack, Riley; Garcia Fernandez, Pablo; Alarcón Cot, Eduardo José; Popoviç, Zoya; Maksimovic, Dragan no pulse shaping methods, Pulsed power supplies, radar transmitters The final radiofrequency power amplifier (PA) of a radar transmitter module is a large factor in system efficiency. Typical radar transmitter signals are frequency-modulated with constant-amplitude pulse envelopes in order to optimize efficiency, resulting in spectral broadening and power radiated outside of the radar frequency band. This paper demonstrates a PA with a dynamic power supply which enables high efficiency while reducing the spectral emissions. The resonant pulse-shaping power supply generates a raised-cosine pulse envelope waveform with efficiency greater than 90% and peak envelope power around 6 W. Measured results with a 2.14-GHz GaN power amplifier with an efficiency of 76% at peak power demonstrate over 67% transmitter efficiency. http://hdl.handle.net/2117/19332 Title: CMOS fast transient low-dropout regulator Authors: Saberkari, Alireza; Alarcón Cot, Eduardo José; Shokouhi, Shahriar B. Abstract: In this paper a fast transient response CFA-based low-dropout regulator (LDO) is introduced. The circuit is stable for 0-100mA output load current and a 1μF output capacitor without any internal compensation. The CFA consists of a voltage follower with output local current-current feedback based on a level-shifted flipped voltage follower (LSFVF) which is instrumental to achieve high regulation and fast transient response. The inverting output buffer stage of the CFA together with current-mirror-based driving of the pass transistor results in high PSRR. Full transistor-level simulation results for an AMS 0.35μm CMOS process design reveal that the proposed LDO dissipates 58μA quiescent current at no-load condition and in worst case conditions has a current efficiency of 99.8%. For a 1μF output capacitor, the maximum output voltage variation to a 0-100mA load transient with rise and fall time of 10 and 100ns is only 2.5mV, and the PSRR is smaller than -58dB over the entire load current range. Fri, 17 May 2013 12:16:56 GMT http://hdl.handle.net/2117/19332 2013-05-17T12:16:56Z Saberkari, Alireza; Alarcón Cot, Eduardo José; Shokouhi, Shahriar B. no fast transient, level-shifted flipped voltage follower, low-dropout In this paper a fast transient response CFA-based low-dropout regulator (LDO) is introduced. The circuit is stable for 0-100mA output load current and a 1μF output capacitor without any internal compensation. The CFA consists of a voltage follower with output local current-current feedback based on a level-shifted flipped voltage follower (LSFVF) which is instrumental to achieve high regulation and fast transient response. The inverting output buffer stage of the CFA together with current-mirror-based driving of the pass transistor results in high PSRR. Full transistor-level simulation results for an AMS 0.35μm CMOS process design reveal that the proposed LDO dissipates 58μA quiescent current at no-load condition and in worst case conditions has a current efficiency of 99.8%. For a 1μF output capacitor, the maximum output voltage variation to a 0-100mA load transient with rise and fall time of 10 and 100ns is only 2.5mV, and the PSRR is smaller than -58dB over the entire load current range. http://hdl.handle.net/2117/19295 Title: Nondestructive diagnosis of mechanical misalignments in dual axis accelerometers Authors: Gómez Pau, Álvaro; Balado Suárez, Luz María; Figueras Pàmies, Joan Abstract: Microelectromechanical systems production is still an immature technology compared to the classical semiconductor industry. MEMS fabrication and packaging processes may present misalignments which result in an improper placement of the internal microstructures or dies. In this work, the possibilities of diagnosing mechanical misalignments of dual axis IC accelerometers are explored. The used method dynamically correlates the two output signals in orthogonal directions. This leads to a Lissajous composition which is able to manifest the actual level of misalignment. The definition of a metric and its variation rate study allows the diagnosis procedure. Experimental results using a commercial dual axis capacitive accelerometer reveal diagnosis discrepancies as low as 1.1%, therefore showing the viability of the proposal. Thu, 16 May 2013 12:38:28 GMT http://hdl.handle.net/2117/19295 2013-05-16T12:38:28Z Gómez Pau, Álvaro; Balado Suárez, Luz María; Figueras Pàmies, Joan no Microelectromechanical systems production is still an immature technology compared to the classical semiconductor industry. MEMS fabrication and packaging processes may present misalignments which result in an improper placement of the internal microstructures or dies. In this work, the possibilities of diagnosing mechanical misalignments of dual axis IC accelerometers are explored. The used method dynamically correlates the two output signals in orthogonal directions. This leads to a Lissajous composition which is able to manifest the actual level of misalignment. The definition of a metric and its variation rate study allows the diagnosis procedure. Experimental results using a commercial dual axis capacitive accelerometer reveal diagnosis discrepancies as low as 1.1%, therefore showing the viability of the proposal. http://hdl.handle.net/2117/19288 Title: Accurate Bearing Faults Classification based on Statistical-Time Features, Curvilinear Component Analysis and Neural Networks Authors: Delgado Prieto, Miquel; Cirrincione,, Giansalvo; García Espinosa, Antonio; Ortega Redondo, Juan Antonio; Henao, Humberto Abstract: Bearing faults are the commonest form of malfunction associated with electrical machines. So far, the research has been carried out mainly in the detection of localized faults, but the diagnosis of distributed faults is still under development. In this context, this work presents a new scheme for detecting and classifying both kinds of faults. This work deals with a new diagnosis monitoring scheme, which is based on statistical-time features calculated from vibration signal, curvilinear component analysis for compression and visualization of the features behavior and a hierarchical neural network structure for classification. The obtained results from different operation conditions validate the effectiveness and feasibility of the proposed methodology. Thu, 16 May 2013 11:46:14 GMT http://hdl.handle.net/2117/19288 2013-05-16T11:46:14Z Delgado Prieto, Miquel; Cirrincione,, Giansalvo; García Espinosa, Antonio; Ortega Redondo, Juan Antonio; Henao, Humberto no Bearing faults are the commonest form of malfunction associated with electrical machines. So far, the research has been carried out mainly in the detection of localized faults, but the diagnosis of distributed faults is still under development. In this context, this work presents a new scheme for detecting and classifying both kinds of faults. This work deals with a new diagnosis monitoring scheme, which is based on statistical-time features calculated from vibration signal, curvilinear component analysis for compression and visualization of the features behavior and a hierarchical neural network structure for classification. The obtained results from different operation conditions validate the effectiveness and feasibility of the proposed methodology. http://hdl.handle.net/2117/19280 Title: A novel condition monitoring scheme for bearing faults based on Curvilinear Component Analysis and hierarchical neural networks Authors: Delgado Prieto, Miquel; Cirrincione,, Giansalvo; García Espinosa, Antonio; Ortega Redondo, Juan Antonio; Henao, Humberto Abstract: Mostly the faults in electrical machines are related with the bearings. Thus, a reliable bearing condition monitoring scheme able to detect either local or distributed defects are mandatory to avoid a breakdown in the machine. So far, the research has been carried out mainly in the detection of local faults, such as balls and raceways faults, but surface roughness is not so reported. This paper deals with a novel and reliable scheme capable to detect any fault that may occur in a bearing, based on EXIN Curvilinear Component Analysis, CCA, and Neural Network. The EXIN CCA, which is an improvement of the Curvilinear Component Analysis, has been conceived for data visualization, interpretation and classification for real time industrial applications. The effectiveness of this condition monitoring scheme has been verified by experimental results obtained from different operation conditions. Thu, 16 May 2013 09:59:44 GMT http://hdl.handle.net/2117/19280 2013-05-16T09:59:44Z Delgado Prieto, Miquel; Cirrincione,, Giansalvo; García Espinosa, Antonio; Ortega Redondo, Juan Antonio; Henao, Humberto no Mostly the faults in electrical machines are related with the bearings. Thus, a reliable bearing condition monitoring scheme able to detect either local or distributed defects are mandatory to avoid a breakdown in the machine. So far, the research has been carried out mainly in the detection of local faults, such as balls and raceways faults, but surface roughness is not so reported. This paper deals with a novel and reliable scheme capable to detect any fault that may occur in a bearing, based on EXIN Curvilinear Component Analysis, CCA, and Neural Network. The EXIN CCA, which is an improvement of the Curvilinear Component Analysis, has been conceived for data visualization, interpretation and classification for real time industrial applications. The effectiveness of this condition monitoring scheme has been verified by experimental results obtained from different operation conditions. http://hdl.handle.net/2117/19262 Title: STLF in the user-side for an iEMS based on evolutionary training of adaptive networks Authors: Cárdenas Araújo, Juan José; Giacometto Torres, Francisco; García Espinosa, Antonio; Romeral Martínez, José Luis Abstract: It is a fact that the short-term load forecasting (STLF)in the user side is growing interest. Consequently, intelligent energy management systems (iEMSs) are including this capability in order to take autonomous decisions. In this context, this paper presents a new STLF scheme based on Adaptative Networks Fuzzy Inference Systems (ANFIS). This ANFIS has an exponential output membership functions (e-ANFIS) and has been trained by means of a novel evolutionary training algorithm (ETA). Due to the computational burden required by ETA, parallel computing was used to eliminate this problem especially for embedded applications. This new scheme has been tested with real data from an automotive factory and it shows better results in comparison with typical adaptative network structures (neural network and ANFIS). Wed, 15 May 2013 15:19:10 GMT http://hdl.handle.net/2117/19262 2013-05-15T15:19:10Z Cárdenas Araújo, Juan José; Giacometto Torres, Francisco; García Espinosa, Antonio; Romeral Martínez, José Luis no It is a fact that the short-term load forecasting (STLF)in the user side is growing interest. Consequently, intelligent energy management systems (iEMSs) are including this capability in order to take autonomous decisions. In this context, this paper presents a new STLF scheme based on Adaptative Networks Fuzzy Inference Systems (ANFIS). This ANFIS has an exponential output membership functions (e-ANFIS) and has been trained by means of a novel evolutionary training algorithm (ETA). Due to the computational burden required by ETA, parallel computing was used to eliminate this problem especially for embedded applications. This new scheme has been tested with real data from an automotive factory and it shows better results in comparison with typical adaptative network structures (neural network and ANFIS). http://hdl.handle.net/2117/19172 Title: New strategy to minimize dead-time distortion in DCI-NPC power amplifiers using COE-error injection Authors: Resano, Tomas; Sala Caselles, Vicenç; Romeral Martínez, José Luis; Moreno Eguilaz, Juan Manuel Abstract: The DCI-NPC topology has become one of the best options to optimize energy efficiency in the world of high power and high quality amplifiers. This can use an analog PWM modulator that is sensitive to generate distortion or error, mainly for two reasons: Carriers Amplitude Error (CAE) and Carriers Offset Error (COE). Other main error and distortion sources in the system is the Dead-Time (td). This is necessary to guarantee the proper operation of the power amplifier stage so that errors and distortions originated by it are unavoidable. This work proposes a negative COE generation to minimize the distortion effects of td. Simulation and experimental results validates this strategy. Mon, 13 May 2013 08:48:31 GMT http://hdl.handle.net/2117/19172 2013-05-13T08:48:31Z Resano, Tomas; Sala Caselles, Vicenç; Romeral Martínez, José Luis; Moreno Eguilaz, Juan Manuel no Amplifiers, Transducers, Equipment The DCI-NPC topology has become one of the best options to optimize energy efficiency in the world of high power and high quality amplifiers. This can use an analog PWM modulator that is sensitive to generate distortion or error, mainly for two reasons: Carriers Amplitude Error (CAE) and Carriers Offset Error (COE). Other main error and distortion sources in the system is the Dead-Time (td). This is necessary to guarantee the proper operation of the power amplifier stage so that errors and distortions originated by it are unavoidable. This work proposes a negative COE generation to minimize the distortion effects of td. Simulation and experimental results validates this strategy. http://hdl.handle.net/2117/19170 Title: Evaluation of trr distorting effects reduction in DCI-NPC multilevel power amplifiers by using SiC diodes and MOSFET technologies Authors: Sala Caselles, Vicenç; Resano, Tomas; Romeral Martínez, José Luis; Moreno Eguilaz, Juan Manuel Abstract: In the last decade, the Power Amplifier applications have used multilevel diode-clamped-inverter or neutral-point-clamped (DCI-NPC) topologies to present very low distortion at high power. In these applications a lot of research has been done in order to reduce the sources of distortion in the DCI-NPC topologies. One of the most important sources of distortion, and less studied, is the reverse recovery time (trr) of the clamp diodes and MOSFET parasitic diodes. Today, with the emergence of Silicon Carbide (SiC) technologies, these sources of distortion are minimized. This paper presents a comparative study and evaluation of the distortion generated by different combinations of diodes and MOSFETs with Si and SiC technologies in a DCI-NPC multilevel Power Amplifier in order to reduce the distortions generated by the non-idealities of the semiconductor devices. Mon, 13 May 2013 08:41:23 GMT http://hdl.handle.net/2117/19170 2013-05-13T08:41:23Z Sala Caselles, Vicenç; Resano, Tomas; Romeral Martínez, José Luis; Moreno Eguilaz, Juan Manuel no Amplifiers, Transducers, Equipment In the last decade, the Power Amplifier applications have used multilevel diode-clamped-inverter or neutral-point-clamped (DCI-NPC) topologies to present very low distortion at high power. In these applications a lot of research has been done in order to reduce the sources of distortion in the DCI-NPC topologies. One of the most important sources of distortion, and less studied, is the reverse recovery time (trr) of the clamp diodes and MOSFET parasitic diodes. Today, with the emergence of Silicon Carbide (SiC) technologies, these sources of distortion are minimized. This paper presents a comparative study and evaluation of the distortion generated by different combinations of diodes and MOSFETs with Si and SiC technologies in a DCI-NPC multilevel Power Amplifier in order to reduce the distortions generated by the non-idealities of the semiconductor devices. http://hdl.handle.net/2117/19159 Title: Fault-tolerance capacity of the multilevel active clamped topology Authors: Nicolás Apruzzese, Joan; Busquets Monge, Sergio; Bordonau Farrerons, José; Alepuz Menéndez, Salvador; Calle Prado, Alejandro Abstract: Thanks to the inherent redundancy to generate the different output voltage levels, the multilevel active clamped (MAC) topology presents an important fault-tolerance ability which makes it interesting for several applications. This paper presents an analysis of the fault-tolerance capacity of the MAC converter. Both open-circuit and short-circuit faults are considered and the analysis is carried out under single-device and two-simultaneous-device faults. Switching strategies to overcome the limitations caused by faults are proposed. Experimental tests with a four-level MAC prototype are presented to validate the analysis. Fri, 10 May 2013 13:04:20 GMT http://hdl.handle.net/2117/19159 2013-05-10T13:04:20Z Nicolás Apruzzese, Joan; Busquets Monge, Sergio; Bordonau Farrerons, José; Alepuz Menéndez, Salvador; Calle Prado, Alejandro no CONVERTER Thanks to the inherent redundancy to generate the different output voltage levels, the multilevel active clamped (MAC) topology presents an important fault-tolerance ability which makes it interesting for several applications. This paper presents an analysis of the fault-tolerance capacity of the MAC converter. Both open-circuit and short-circuit faults are considered and the analysis is carried out under single-device and two-simultaneous-device faults. Switching strategies to overcome the limitations caused by faults are proposed. Experimental tests with a four-level MAC prototype are presented to validate the analysis. http://hdl.handle.net/2117/19146 Title: Dynamic behaviour of a back-to-back five-level flying capacitor converter with reduced DC bus capacitance Authors: Ghias, A.M.Y.M.; Ciobotaru, M.; Agelidis, Vassilios; Pou Félix, Josep Abstract: Due to extensive research, advanced voltage source converter (VSC) such as multilevel and multi-module have been proposed for high power applications. These advanced VSCs must provide secure as well as, intelligent power management operation for the future electricity network under various grid events. The focus of this paper is to evaluate the dynamic performance of a back-to-back five-level flying capacitor (FC) converter system with reduced DC bus capacitance under different grid voltage disturbances. The system uses a classical synchronous reference frame control technique for active/reactive power control and DC voltage regulation, and is tested in terms of general grid events such as power flow reversal, voltage amplitude excursions, phase jumps and frequency variations using MATLAB/Simulink and PLECS blockset. The simulation results show that the back-to-back FC converter with reduced DC bus capacitance performs well during the mentioned grid events. Thu, 09 May 2013 10:53:47 GMT http://hdl.handle.net/2117/19146 2013-05-09T10:53:47Z Ghias, A.M.Y.M.; Ciobotaru, M.; Agelidis, Vassilios; Pou Félix, Josep no Analysis and Simulations, FC converter, Grid Conditions, Grid voltage disturbances, Multilevel converter, Power Quality Due to extensive research, advanced voltage source converter (VSC) such as multilevel and multi-module have been proposed for high power applications. These advanced VSCs must provide secure as well as, intelligent power management operation for the future electricity network under various grid events. The focus of this paper is to evaluate the dynamic performance of a back-to-back five-level flying capacitor (FC) converter system with reduced DC bus capacitance under different grid voltage disturbances. The system uses a classical synchronous reference frame control technique for active/reactive power control and DC voltage regulation, and is tested in terms of general grid events such as power flow reversal, voltage amplitude excursions, phase jumps and frequency variations using MATLAB/Simulink and PLECS blockset. The simulation results show that the back-to-back FC converter with reduced DC bus capacitance performs well during the mentioned grid events. http://hdl.handle.net/2117/19145 Title: Performance evaluation of a five-level flying capacitor converter with reduced DC bus capacitance under two different modulation schemes Authors: Ghias, A.M.Y.M.; Pou Félix, Josep; Ciobotaru, M.; Agelidis, Vassilios Abstract: In flying capacitor (FC) converters, phase-shifted pulse-width modulation (PS-PWM) provides natural voltage balancing. However, for a practical application, a more robust balancing mechanism of maintaining the FC voltages at the desired values is required. This paper proposes a new closed-loop voltage balancing method for multilevel FC converters using PSPWM. The proposed method balances the voltages of the FCs by modifying the duty cycle of each switch of the FC converter using a proportional (P) controller. The crossed effect between FC currents and duty cycles is considered and is used for FC voltage balancing. The Simulation results verify that the proposed voltage balancing method is very robust to different operating conditions, such as load transients and non-linear loads. Thu, 09 May 2013 10:39:17 GMT http://hdl.handle.net/2117/19145 2013-05-09T10:39:17Z Ghias, A.M.Y.M.; Pou Félix, Josep; Ciobotaru, M.; Agelidis, Vassilios no AC/DC converters, Back-to-back system, DC/AC converters, FC multilevel converters, PD-PWM, PS-PWM, Reduced DC-link capacitor, Voltage balancing strategy In flying capacitor (FC) converters, phase-shifted pulse-width modulation (PS-PWM) provides natural voltage balancing. However, for a practical application, a more robust balancing mechanism of maintaining the FC voltages at the desired values is required. This paper proposes a new closed-loop voltage balancing method for multilevel FC converters using PSPWM. The proposed method balances the voltages of the FCs by modifying the duty cycle of each switch of the FC converter using a proportional (P) controller. The crossed effect between FC currents and duty cycles is considered and is used for FC voltage balancing. The Simulation results verify that the proposed voltage balancing method is very robust to different operating conditions, such as load transients and non-linear loads. http://hdl.handle.net/2117/19144 Title: Clamping diode caused distortion in multilevel NPC Full-Bridge audio power amplifiers Authors: Sala Caselles, Vicenç; Salehi Arashloo Arashloo, Ramin; Moreno Eguilaz, Juan Manuel; Salehifar, Mehdi; Romeral Martínez, José Luis Abstract: This paper presents a study and analysis of the distorting effects of clamped diodes in multilevel DCI-NPC topology applied to high power and high quality audio-amplifier. The main distorting sources of error are characterized, which are due to the clamped-diodes non-idealities; and they are evaluated for typical commercial diodes values and working conditions. Through this study the distorting contribution of each non-ideality can be quantified, and the influence of the system operating parameters, such as reactive current angle and modulation index, are highlighted. Finally, it is presented the table of optimal parameters that a commercial diode should have to ensure proper operation of the amplifier under rated power and quality specification. Thu, 09 May 2013 10:36:55 GMT http://hdl.handle.net/2117/19144 2013-05-09T10:36:55Z Sala Caselles, Vicenç; Salehi Arashloo Arashloo, Ramin; Moreno Eguilaz, Juan Manuel; Salehifar, Mehdi; Romeral Martínez, José Luis no Audio-frequency amplifiers; Diodes; Distortion; Modulation; Power amplifiers This paper presents a study and analysis of the distorting effects of clamped diodes in multilevel DCI-NPC topology applied to high power and high quality audio-amplifier. The main distorting sources of error are characterized, which are due to the clamped-diodes non-idealities; and they are evaluated for typical commercial diodes values and working conditions. Through this study the distorting contribution of each non-ideality can be quantified, and the influence of the system operating parameters, such as reactive current angle and modulation index, are highlighted. Finally, it is presented the table of optimal parameters that a commercial diode should have to ensure proper operation of the amplifier under rated power and quality specification. http://hdl.handle.net/2117/19136 Title: EMI performance comparison of two-level and three-level inverters in small dc-link capacitors based motor drives Authors: Maheshwari, RamKrishan; Munk-Nielsen, Stig; Busquets Monge, Sergio Abstract: The size of passive components in an adjustable speed drive can be reduced by using small dc-link capacitors. The EMI filter in the drive also consists of passive components. The size of the filter can be reduced by using a three-level inverter, which can have low output voltage distortion. However, the three-level inverter based on small dc-link capacitors requires a PWM strategy to maintain neutral-point voltage balance. In this paper, the common mode voltage, which is the determining factor for the EMI filter size, is analyzed for a virtual-vector-based PWM strategy. The common mode voltage, the shaft voltage, and the conducted emission for the small dc-link capacitor based three-level inverter are compared with that of the two-level inverter operated with space vector PWM strategy. Experimental results for the common mode voltage, the shaft voltage, and the conducted emission are presented. Results show that the conducted emission from the three-level inverter is lower than that of the two-level inverter. Thus, a three-level inverter requires a smaller EMI filter in motor drives with small dc-link capacitors. Wed, 08 May 2013 13:38:15 GMT http://hdl.handle.net/2117/19136 2013-05-08T13:38:15Z Maheshwari, RamKrishan; Munk-Nielsen, Stig; Busquets Monge, Sergio no Adjustable speed drives, Common mode voltage, Conducted emissions, Dc link capacitor, EMI filters, Low output voltage, Motor drive, Neutral-point voltages, Passive components, Performance comparison, PWM strategy, Shaft voltage, Space vector PWM, Three-level inverters The size of passive components in an adjustable speed drive can be reduced by using small dc-link capacitors. The EMI filter in the drive also consists of passive components. The size of the filter can be reduced by using a three-level inverter, which can have low output voltage distortion. However, the three-level inverter based on small dc-link capacitors requires a PWM strategy to maintain neutral-point voltage balance. In this paper, the common mode voltage, which is the determining factor for the EMI filter size, is analyzed for a virtual-vector-based PWM strategy. The common mode voltage, the shaft voltage, and the conducted emission for the small dc-link capacitor based three-level inverter are compared with that of the two-level inverter operated with space vector PWM strategy. Experimental results for the common mode voltage, the shaft voltage, and the conducted emission are presented. Results show that the conducted emission from the three-level inverter is lower than that of the two-level inverter. Thus, a three-level inverter requires a smaller EMI filter in motor drives with small dc-link capacitors.