http://hdl.handle.net/2117/3644 Thu, 23 May 2013 11:55:24 GMT 2013-05-23T11:55:24Z webmaster.bupc@upc.edu Universitat Politècnica de Catalunya. Servei de Biblioteques i Documentació no http://hdl.handle.net/2117/19295 Title: Nondestructive diagnosis of mechanical misalignments in dual axis accelerometers Authors: Gómez Pau, Álvaro; Balado Suárez, Luz María; Figueras Pàmies, Joan Abstract: Microelectromechanical systems production is still an immature technology compared to the classical semiconductor industry. MEMS fabrication and packaging processes may present misalignments which result in an improper placement of the internal microstructures or dies. In this work, the possibilities of diagnosing mechanical misalignments of dual axis IC accelerometers are explored. The used method dynamically correlates the two output signals in orthogonal directions. This leads to a Lissajous composition which is able to manifest the actual level of misalignment. The definition of a metric and its variation rate study allows the diagnosis procedure. Experimental results using a commercial dual axis capacitive accelerometer reveal diagnosis discrepancies as low as 1.1%, therefore showing the viability of the proposal. Thu, 16 May 2013 12:38:28 GMT http://hdl.handle.net/2117/19295 2013-05-16T12:38:28Z Gómez Pau, Álvaro; Balado Suárez, Luz María; Figueras Pàmies, Joan no Microelectromechanical systems production is still an immature technology compared to the classical semiconductor industry. MEMS fabrication and packaging processes may present misalignments which result in an improper placement of the internal microstructures or dies. In this work, the possibilities of diagnosing mechanical misalignments of dual axis IC accelerometers are explored. The used method dynamically correlates the two output signals in orthogonal directions. This leads to a Lissajous composition which is able to manifest the actual level of misalignment. The definition of a metric and its variation rate study allows the diagnosis procedure. Experimental results using a commercial dual axis capacitive accelerometer reveal diagnosis discrepancies as low as 1.1%, therefore showing the viability of the proposal. http://hdl.handle.net/2117/17947 Title: Built-In test of MEMS capacitive accelerometers for field failures and aging degradation. Authors: Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suárez, Luz María; Figueras Pàmies, Joan Fri, 22 Feb 2013 14:42:57 GMT http://hdl.handle.net/2117/17947 2013-02-22T14:42:57Z Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suárez, Luz María; Figueras Pàmies, Joan no http://hdl.handle.net/2117/17943 Title: SRAM stability metric under transient noise Authors: Vatajelu, Elena Ioana; Gómez Pau, Álvaro; Renovell, Michel; Figueras Pàmies, Joan Abstract: ventional way to analyze the robustness of an SRAM bit cell is to quantify its immunity to static noise. The static immunity to disturbances like process and mi smatch variations, bulk noises, supply rings variations, temperature changes is well characterized by means of the Static Noise Margin (SNM) defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes. However, a significant number of disturbance sources present a transient behavior which is ignored by the static analysis but has to be taken in consideration for a complete characterization of the cell’s behavior. In this paper, a metric to evaluate the cell robustness in the presence of transient voltage noise is proposed based on determining the energy of the noise signal which is able to flip the cell’s state. The Dynamic Noise Margin(DNM) metric is defined as the minimum energy of the voltage noise signal able to flip the cell. Fri, 22 Feb 2013 13:45:26 GMT http://hdl.handle.net/2117/17943 2013-02-22T13:45:26Z Vatajelu, Elena Ioana; Gómez Pau, Álvaro; Renovell, Michel; Figueras Pàmies, Joan no ventional way to analyze the robustness of an SRAM bit cell is to quantify its immunity to static noise. The static immunity to disturbances like process and mi smatch variations, bulk noises, supply rings variations, temperature changes is well characterized by means of the Static Noise Margin (SNM) defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes. However, a significant number of disturbance sources present a transient behavior which is ignored by the static analysis but has to be taken in consideration for a complete characterization of the cell’s behavior. In this paper, a metric to evaluate the cell robustness in the presence of transient voltage noise is proposed based on determining the energy of the noise signal which is able to flip the cell’s state. The Dynamic Noise Margin(DNM) metric is defined as the minimum energy of the voltage noise signal able to flip the cell. http://hdl.handle.net/2117/17195 Title: IR-drop in on-chip power distribution networks of ICs with nonuniform power consumption Authors: Rius Vázquez, José Abstract: A compact IR-drop model for on-chip power distribution networks in array and wire-bonded ICs is analyzed. Chip dimensions, size, and location of the supply pads, metal coverage, piecewise distribution of IC consumption, and the resistance between the pads and the power supply are considered to obtain closed-form expressions for the IR-drop. The IR-drop model is validated by comparing its results with electrical simulations. The obtained error is in the range of 1%. Mon, 07 Jan 2013 11:20:43 GMT http://hdl.handle.net/2117/17195 2013-01-07T11:20:43Z Rius Vázquez, José no A compact IR-drop model for on-chip power distribution networks in array and wire-bonded ICs is analyzed. Chip dimensions, size, and location of the supply pads, metal coverage, piecewise distribution of IC consumption, and the resistance between the pads and the power supply are considered to obtain closed-form expressions for the IR-drop. The IR-drop model is validated by comparing its results with electrical simulations. The obtained error is in the range of 1%. http://hdl.handle.net/2117/16824 Title: Optimization of oxygen transfer through venturi-based systems applied to the biological sweetening of biogas Authors: Rodriguez, Ginesta; Dorado Castaño, Antonio David; Bonsfills Pedrós, Anna; Sanahuja Moliner, Ricard; Gabriel, David; Gamisans Noguera, Javier Wed, 31 Oct 2012 11:49:52 GMT http://hdl.handle.net/2117/16824 2012-10-31T11:49:52Z Rodriguez, Ginesta; Dorado Castaño, Antonio David; Bonsfills Pedrós, Anna; Sanahuja Moliner, Ricard; Gabriel, David; Gamisans Noguera, Javier no Biogas desulfurization, Biotrickling filters, Diffuser, Jet-venturi, Mass transfer, Venturi ejector http://hdl.handle.net/2117/15781 Title: Transient noise failures in SRAM cells: dynamic noise margin metric Authors: Vatajelu, Elena Ioana; Gómez Pau, Álvaro; Renovell, Michel; Figueras Pàmies, Joan Abstract: Current nanometric IC processes need to assess the robustness of memories under any possible source of disturbance: process and mismatch variations, bulk noises, supply rings variations, temperature changes, aging and environmental aggressions such as RF or on-chip couplings. In the case of SRAM cells, the static immunity to such perturbations is well characterized by means of the Static Noise Margin (SNM)defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes. In addition, a significant number of disturbance sources present a transient behavior which has to be taken in consideration. In this paper, a metric to evaluate the cell robustness in the presence of transient voltage signals is proposed. Sufficiently high energy noise signals will compel the cell to flip to a failure state. On the other hand, sufficiently low energy noise signals will not be able to flip the cell and the state will be preserved. The Dynamic Noise Margin(DNM) metric is defined as the minimum energy of the voltage pulses able to flip the cell. A case example of transient voltage noise pulses on a 6T SRAM cell using 45nm technology has been studied. Simulation results show the use of the proposed metric as an indicator of cell robustness in the presence of transient voltage noise Mon, 07 May 2012 09:57:32 GMT http://hdl.handle.net/2117/15781 2012-05-07T09:57:32Z Vatajelu, Elena Ioana; Gómez Pau, Álvaro; Renovell, Michel; Figueras Pàmies, Joan no Current nanometric IC processes need to assess the robustness of memories under any possible source of disturbance: process and mismatch variations, bulk noises, supply rings variations, temperature changes, aging and environmental aggressions such as RF or on-chip couplings. In the case of SRAM cells, the static immunity to such perturbations is well characterized by means of the Static Noise Margin (SNM)defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes. In addition, a significant number of disturbance sources present a transient behavior which has to be taken in consideration. In this paper, a metric to evaluate the cell robustness in the presence of transient voltage signals is proposed. Sufficiently high energy noise signals will compel the cell to flip to a failure state. On the other hand, sufficiently low energy noise signals will not be able to flip the cell and the state will be preserved. The Dynamic Noise Margin(DNM) metric is defined as the minimum energy of the voltage pulses able to flip the cell. A case example of transient voltage noise pulses on a 6T SRAM cell using 45nm technology has been studied. Simulation results show the use of the proposed metric as an indicator of cell robustness in the presence of transient voltage noise http://hdl.handle.net/2117/15667 Title: Process variability in sub-16nm bulk CMOS technology Authors: Rubio Sola, Jose Antonio; Figueras Pàmies, Joan; Vatajelu, Elena Ioana; Canal Corretger, Ramon Abstract: The document is part of deliverable D3.6 of the TRAMS Project (EU FP7 248789), of public nature, and shows and justifies the levels of variability used in the research project for sub-18nm bulk CMOS technologies. Mon, 26 Mar 2012 18:45:53 GMT http://hdl.handle.net/2117/15667 2012-03-26T18:45:53Z Rubio Sola, Jose Antonio; Figueras Pàmies, Joan; Vatajelu, Elena Ioana; Canal Corretger, Ramon no The document is part of deliverable D3.6 of the TRAMS Project (EU FP7 248789), of public nature, and shows and justifies the levels of variability used in the research project for sub-18nm bulk CMOS technologies. http://hdl.handle.net/2117/15090 Title: Lecturer and student perceptions on CLIL at a spanish university Authors: Aguilar Pérez, Marta; Rodríguez Montañés, Rosa Abstract: This study reports on a pilot implementation of Content and Language Integrated Learning (CLIL) at a Spanish university. In order to find out how both lecturers and students perceived their experience, several interviews and meetings took place with lecturers, and an open-ended questionnaire was passed to students. The meetings and interviews with lecturers yielded important information about their satisfaction. It was found out that lecturers were mostly interested in practising and improving their English spoken fluency, they did not feel that the quality of their teaching had been sacrificed, they had not included any question on language learning in their assessment and they showed great reluctance to receiving any CLIL methodological training. As to students’ reactions, analysis of their questionnaires revealed that most of them found the experience positive. Their self-reported perceived gains unanimously point to the specialised vocabulary they have learnt and, in the second place, to an improvement of their listening and speaking skills. The most outstanding negative aspect they found is lecturers’ insufficient level of English. CLIL training specially adapted to university teachers is necessary so that lecturers can overcome their reluctance to a methodological training and thereby the potential of CLIL is realised. Mon, 13 Feb 2012 12:04:55 GMT http://hdl.handle.net/2117/15090 2012-02-13T12:04:55Z Aguilar Pérez, Marta; Rodríguez Montañés, Rosa no This study reports on a pilot implementation of Content and Language Integrated Learning (CLIL) at a Spanish university. In order to find out how both lecturers and students perceived their experience, several interviews and meetings took place with lecturers, and an open-ended questionnaire was passed to students. The meetings and interviews with lecturers yielded important information about their satisfaction. It was found out that lecturers were mostly interested in practising and improving their English spoken fluency, they did not feel that the quality of their teaching had been sacrificed, they had not included any question on language learning in their assessment and they showed great reluctance to receiving any CLIL methodological training. As to students’ reactions, analysis of their questionnaires revealed that most of them found the experience positive. Their self-reported perceived gains unanimously point to the specialised vocabulary they have learnt and, in the second place, to an improvement of their listening and speaking skills. The most outstanding negative aspect they found is lecturers’ insufficient level of English. CLIL training specially adapted to university teachers is necessary so that lecturers can overcome their reluctance to a methodological training and thereby the potential of CLIL is realised. http://hdl.handle.net/2117/14651 Title: Maximum IR-drop in On-Chip Power Distribution Networks of Wire-Bonded Integrated Circuits Authors: Rius Vázquez, José; Aguareles Carrero, María Abstract: A compact IR-drop model for on-chip power distribution networks in wire-bonded ICs is presented. Chip dimensions, metal coverage and piecewise distribution of the IC consumption are taken into account to obtain closed form expressions for the maximum IR-drop as well as its place. Comparison with simulations shows an error as small as 2% in most the cases. Wed, 18 Jan 2012 12:46:01 GMT http://hdl.handle.net/2117/14651 2012-01-18T12:46:01Z Rius Vázquez, José; Aguareles Carrero, María no A compact IR-drop model for on-chip power distribution networks in wire-bonded ICs is presented. Chip dimensions, metal coverage and piecewise distribution of the IC consumption are taken into account to obtain closed form expressions for the maximum IR-drop as well as its place. Comparison with simulations shows an error as small as 2% in most the cases. http://hdl.handle.net/2117/14597 Title: 8T SRAM Cell with Open Defects under Voltage and Timing Variations Authors: Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pàmies, Joan; Castillo Muñoz, Raul Tue, 17 Jan 2012 12:01:26 GMT http://hdl.handle.net/2117/14597 2012-01-17T12:01:26Z Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pàmies, Joan; Castillo Muñoz, Raul no http://hdl.handle.net/2117/14355 Title: Identification of component deviations in analog circuits using digital signatures Authors: Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suárez, Luz María; Figueras Pàmies, Joan Abstract: Analog circuits component diagnosis is a challenging task requiring expensive resources. This paper presents a low cost method to identify deviations in multiple component values using a precharacterisation of the impact of the deviations on the digital signatures for a set of input excitations. The method predicts several circuit under diagnosis (CUD) deviations by mapping them to a scalar value that indicates the discrepancy of the defective and golden digital signatures. Input excitation consists of a small set of sinusoidal signals with different frequencies. A digital signature is generated for every excitation set and compared to the golden response. The scalar discrepancy values are used to obtain the component deviations of the CUD. In order to generate the signatures, a CMOS monitor circuit has been designed and fabricated. The method is applied to the identification of capacitance deviations in a Biquad filter. Simulated results show the possibilities of the proposal Thu, 29 Dec 2011 12:18:05 GMT http://hdl.handle.net/2117/14355 2011-12-29T12:18:05Z Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suárez, Luz María; Figueras Pàmies, Joan no Analog circuits component diagnosis is a challenging task requiring expensive resources. This paper presents a low cost method to identify deviations in multiple component values using a precharacterisation of the impact of the deviations on the digital signatures for a set of input excitations. The method predicts several circuit under diagnosis (CUD) deviations by mapping them to a scalar value that indicates the discrepancy of the defective and golden digital signatures. Input excitation consists of a small set of sinusoidal signals with different frequencies. A digital signature is generated for every excitation set and compared to the golden response. The scalar discrepancy values are used to obtain the component deviations of the CUD. In order to generate the signatures, a CMOS monitor circuit has been designed and fabricated. The method is applied to the identification of capacitance deviations in a Biquad filter. Simulated results show the possibilities of the proposal http://hdl.handle.net/2117/13394 Title: Testing IC accelerometers using Lissajous compositions Authors: Gómez Pau, Álvaro; Balado Suárez, Luz María; Figueras Pàmies, Joan Abstract: Micro Electro Mechanical devices (MEMs) have widened their range of applications in a spectacular way in the last years. Reliability of MEMs devices is one of the areas that need to be improved to achieve high volume production at allowable costs. Accelerometers have in their design some mechanical and layout symmetries that can be used to improve the test and diagnosis results. In our approach we take profit of the symmetries of dual axis accelerometers to analyze and test its behavior using a procedure that composes the two orthogonal outputs when the accelerometer is spun. The complexity in the kinematics seen by the sensitive axes of the accelerometer yields rich and complex Lissajous traces that characterize the device and allows to determine the possible mismatchings in the assumed damped mass model parameters. In order to compare and quantify parameter discrepancies, a metric has been defined to allow to determine whether the DUT is within specifications or not. Thu, 29 Sep 2011 16:46:04 GMT http://hdl.handle.net/2117/13394 2011-09-29T16:46:04Z Gómez Pau, Álvaro; Balado Suárez, Luz María; Figueras Pàmies, Joan no Micro Electro Mechanical devices (MEMs) have widened their range of applications in a spectacular way in the last years. Reliability of MEMs devices is one of the areas that need to be improved to achieve high volume production at allowable costs. Accelerometers have in their design some mechanical and layout symmetries that can be used to improve the test and diagnosis results. In our approach we take profit of the symmetries of dual axis accelerometers to analyze and test its behavior using a procedure that composes the two orthogonal outputs when the accelerometer is spun. The complexity in the kinematics seen by the sensitive axes of the accelerometer yields rich and complex Lissajous traces that characterize the device and allows to determine the possible mismatchings in the assumed damped mass model parameters. In order to compare and quantify parameter discrepancies, a metric has been defined to allow to determine whether the DUT is within specifications or not. http://hdl.handle.net/2117/13378 Title: CLIL implementation at a Spanish university: A pilot experience Authors: Aguilar Pérez, Marta; Rodríguez Montañés, Rosa; Oriol, Carlos Wed, 28 Sep 2011 11:39:43 GMT http://hdl.handle.net/2117/13378 2011-09-28T11:39:43Z Aguilar Pérez, Marta; Rodríguez Montañés, Rosa; Oriol, Carlos no http://hdl.handle.net/2117/12696 Title: Gate leakage impact on full open defects in interconnect lines Authors: Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan; Eichenberger, Stefan; Hora, Camelia; Kruseman, Bram Abstract: An Interconnect full open defect breaks the connection between the driver and the gate terminals of downstream transistors, generating a floating line. The behavior of floating lines is known to depend on several factors, namely parasitic capacitances to neighboring structures, transistor capacitances of downstream gate(s) and trapped charges. For nanometer CMOS technologies, the reduction of oxide thickness leads to a significant increase in gate tunneling leakage. This new phenomenon influences the behavior of circuits with interconnect full open defects. Floating lines can no longer be considered electrically isolated and are subjected to transient evolutions, reaching a steady state determined by the technology, downstream interconnect and gate(s) topology. The occurrence of such defects and the impact of gate tunneling leakage are expected to increase in the future. In this work, interconnect full open defects affecting nanometer CMOS technologies are analyzed and the defective logic response of downstream gates after reaching the steady state is predicted. Experimental evidence of this behavior is presented for circuits belonging to a 180 nm and a 65 nm CMOS technologies. Technology trends show that the impact of gate leakage currents is expected to increase in future technologies. Thu, 02 Jun 2011 13:57:25 GMT http://hdl.handle.net/2117/12696 2011-06-02T13:57:25Z Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan; Eichenberger, Stefan; Hora, Camelia; Kruseman, Bram no An Interconnect full open defect breaks the connection between the driver and the gate terminals of downstream transistors, generating a floating line. The behavior of floating lines is known to depend on several factors, namely parasitic capacitances to neighboring structures, transistor capacitances of downstream gate(s) and trapped charges. For nanometer CMOS technologies, the reduction of oxide thickness leads to a significant increase in gate tunneling leakage. This new phenomenon influences the behavior of circuits with interconnect full open defects. Floating lines can no longer be considered electrically isolated and are subjected to transient evolutions, reaching a steady state determined by the technology, downstream interconnect and gate(s) topology. The occurrence of such defects and the impact of gate tunneling leakage are expected to increase in the future. In this work, interconnect full open defects affecting nanometer CMOS technologies are analyzed and the defective logic response of downstream gates after reaching the steady state is predicted. Experimental evidence of this behavior is presented for circuits belonging to a 180 nm and a 65 nm CMOS technologies. Technology trends show that the impact of gate leakage currents is expected to increase in future technologies. http://hdl.handle.net/2117/11989 Title: Defective Behaviour of an 8T SRAM Cell with Open Defects Authors: Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Manich Bou, Salvador; Figueras Pàmies, Joan; Di Carlo, Stefano; Prinetto, Paolo; Scionti, Alberto Mon, 21 Mar 2011 13:55:57 GMT http://hdl.handle.net/2117/11989 2011-03-21T13:55:57Z Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Manich Bou, Salvador; Figueras Pàmies, Joan; Di Carlo, Stefano; Prinetto, Paolo; Scionti, Alberto no