http://hdl.handle.net/2117/3240 Thu, 20 Jun 2013 10:04:42 GMT 2013-06-20T10:04:42Z webmaster.bupc@upc.edu Universitat Politècnica de Catalunya. Servei de Biblioteques i Documentació no http://hdl.handle.net/2117/18574 Title: Fractional DC-DC converter in solar-powered electrical generation systems Authors: Martínez González, Rubén; Bolea Monte, Yolanda; Grau Saldes, Antoni; Martínez García, Herminio Abstract: This paper deals with the fractional modeling of a DC-DC buck-boost converter, suitable in solar-powered electrical generation systems, and the design of a fractional controller for the aforementioned switching converter. Although the modeling and design of the controller is carried out for this particular DC-DC converter, it can be easily extended to other kind of switching converter. In addition, the comparison between integer-order plan/controller and fractional-order plants/controller is carried out. The article also shows that, under the same design conditions, the fractional-order controller has a better performance and behaviour than the classical integer-order controller in both situations, that is, with integer-order plant and fractional-order plant models. Wed, 03 Apr 2013 12:02:03 GMT http://hdl.handle.net/2117/18574 2013-04-03T12:02:03Z Martínez González, Rubén; Bolea Monte, Yolanda; Grau Saldes, Antoni; Martínez García, Herminio no This paper deals with the fractional modeling of a DC-DC buck-boost converter, suitable in solar-powered electrical generation systems, and the design of a fractional controller for the aforementioned switching converter. Although the modeling and design of the controller is carried out for this particular DC-DC converter, it can be easily extended to other kind of switching converter. In addition, the comparison between integer-order plan/controller and fractional-order plants/controller is carried out. The article also shows that, under the same design conditions, the fractional-order controller has a better performance and behaviour than the classical integer-order controller in both situations, that is, with integer-order plant and fractional-order plant models. http://hdl.handle.net/2117/17379 Title: Fractional DC/DC converter in solar–powered electrical generation systems Authors: Martínez, Rubén; Bolea Monte, Yolanda; Grau Saldes, Antoni; Martínez García, Herminio Abstract: This paper deals with the fractional modeling of a DC-DC buck-boost converter, suitable in solar-powered electrical generation systems, and the design of a fractional controller for the aforementioned switching converter. Although the modeling and design of the controller is carried out for this particular DC-DC converter, it can be easily extended to other kind of switching converter. In addition, the comparison between integer-order plant/controller and fractional-order plants/controller is carried out. The article also shows that, under the same design conditions, the fractional-order controller has a better performance and behaviour than the classical integer-order controller in both situations, that is, with integer-order plant and fractional-order plant models Wed, 16 Jan 2013 07:44:11 GMT http://hdl.handle.net/2117/17379 2013-01-16T07:44:11Z Martínez, Rubén; Bolea Monte, Yolanda; Grau Saldes, Antoni; Martínez García, Herminio no This paper deals with the fractional modeling of a DC-DC buck-boost converter, suitable in solar-powered electrical generation systems, and the design of a fractional controller for the aforementioned switching converter. Although the modeling and design of the controller is carried out for this particular DC-DC converter, it can be easily extended to other kind of switching converter. In addition, the comparison between integer-order plant/controller and fractional-order plants/controller is carried out. The article also shows that, under the same design conditions, the fractional-order controller has a better performance and behaviour than the classical integer-order controller in both situations, that is, with integer-order plant and fractional-order plant models http://hdl.handle.net/2117/16474 Title: Instabilities in digitally controlled voltage-mode synchronous buck converter Authors: Dongsheng, Yu; Herbert, H. C. Iu; Hao, Chen; Rodriguez, E.; Alarcón Cot, Eduardo José; El Aroudi, Abdelali Abstract: In this paper, instabilities and bifurcation behavior in a DC–DC digitally controlled voltagemode synchronous buck converter (SBC) are studied. The bifurcation diagram of the system under a proportional-integral (PI) compensation is presented. Following the system mathematical description in the continuous time domain, the z-domain pulse transfer function is derived in terms of system parameters. The stability range of the design parameter is obtained in closed form by using the Jury test combined with the describing function (DF) method. Experimental measurements from a laboratory prototype are used to validate the theoretical predictions and the numerical simulations. Wed, 12 Sep 2012 11:55:34 GMT http://hdl.handle.net/2117/16474 2012-09-12T11:55:34Z Dongsheng, Yu; Herbert, H. C. Iu; Hao, Chen; Rodriguez, E.; Alarcón Cot, Eduardo José; El Aroudi, Abdelali no Buck converter, Digital control, Instability, Limit cycle In this paper, instabilities and bifurcation behavior in a DC–DC digitally controlled voltagemode synchronous buck converter (SBC) are studied. The bifurcation diagram of the system under a proportional-integral (PI) compensation is presented. Following the system mathematical description in the continuous time domain, the z-domain pulse transfer function is derived in terms of system parameters. The stability range of the design parameter is obtained in closed form by using the Jury test combined with the describing function (DF) method. Experimental measurements from a laboratory prototype are used to validate the theoretical predictions and the numerical simulations. http://hdl.handle.net/2117/16468 Title: Power MOSFET technology roadmap toward high power density voltage regulators for next-generation computer processors Authors: López, Toni; Alarcón Cot, Eduardo José Abstract: A synchronous buck converter based multiphase architecture is evaluated to determine whether or not the most widespread voltage regulator (VR) topology canmeet the power delivery requirements of next-generation computer processors. The applied analysis methodology relies on accurate device models for circuit simulations, where the power MOSFETs are central due to their primary relevance to power losses. The method is referred to as virtual design loop and aims at optimizing the overall system performance with minimum empirical efforts. This is successfully applied to the development of a power MOSFET technology offering outstanding dynamic and static performance characteristics in the application. From a system perspective, the limits of power density conversion will be explored for this and other emerging technologies that promise to open up a new paradigm in power integration capabilities. Wed, 12 Sep 2012 09:40:30 GMT http://hdl.handle.net/2117/16468 2012-09-12T09:40:30Z López, Toni; Alarcón Cot, Eduardo José no A synchronous buck converter based multiphase architecture is evaluated to determine whether or not the most widespread voltage regulator (VR) topology canmeet the power delivery requirements of next-generation computer processors. The applied analysis methodology relies on accurate device models for circuit simulations, where the power MOSFETs are central due to their primary relevance to power losses. The method is referred to as virtual design loop and aims at optimizing the overall system performance with minimum empirical efforts. This is successfully applied to the development of a power MOSFET technology offering outstanding dynamic and static performance characteristics in the application. From a system perspective, the limits of power density conversion will be explored for this and other emerging technologies that promise to open up a new paradigm in power integration capabilities. http://hdl.handle.net/2117/15941 Title: Physical channel characterization for medium-range nanonetworks using flagellated bacteria Authors: Gregori, Maria; Llatser Martí, Ignacio; Cabellos Aparicio, Alberto; Alarcón Cot, Eduardo José Abstract: Nano-networks are the interconnection of nano-machines and as such expand the limited capabilities of a single nano-machine. Several techniques have been proposed so far to interconnect nano-machines. For short dis- tances (nm-mm ranges), researchers are proposing to use molecular motors and calcium signaling. For long distances (mm-m), pheromones are envisioned to transport information. In this work we propose a new mechanism for medium-range communications (nm- m): agellated bacteria. This technique is based on the transport of DNA-encoded information between emitters and receivers by means of a bacterium. We present a physical channel characterization and a simulator that, based on the previous characterization, simulates the transmission of a DNA-packet between two nano-machines. Wed, 30 May 2012 08:53:26 GMT http://hdl.handle.net/2117/15941 2012-05-30T08:53:26Z Gregori, Maria; Llatser Martí, Ignacio; Cabellos Aparicio, Alberto; Alarcón Cot, Eduardo José no Nanonetworks, Molecular communication, Flagellated bacteria, DNA packet, Propagation delay Nano-networks are the interconnection of nano-machines and as such expand the limited capabilities of a single nano-machine. Several techniques have been proposed so far to interconnect nano-machines. For short dis- tances (nm-mm ranges), researchers are proposing to use molecular motors and calcium signaling. For long distances (mm-m), pheromones are envisioned to transport information. In this work we propose a new mechanism for medium-range communications (nm- m): agellated bacteria. This technique is based on the transport of DNA-encoded information between emitters and receivers by means of a bacterium. We present a physical channel characterization and a simulator that, based on the previous characterization, simulates the transmission of a DNA-packet between two nano-machines. http://hdl.handle.net/2117/15776 Title: Energy-balance control of PV cascaded multilevel grid-connected inverters for phase-shifted and level-shifted pulse-width modulations Authors: Chavarría Roe, Javier; Biel Solé, Domingo; Guinjoan Gispert, Francisco; Meza Benavides, Carlos; Negroni Vera, Juan José Abstract: This paper presents an energy-balance control strategy for a cascaded single-phase grid-connected H-bridge multilevel inverter linking n independent PV arrays to the grid. The control scheme is based on an energy-sampled data model of the PV system and enables the design of a voltage loop linear discrete controller for each array ensuring the stability of the system for the whole range of PV arrays operating conditions. The control design is adapted to Phase-Shifted and Level-Shifted Carrier PWM to share the control action among the cascadeconnected bridges in order to concurrently synthesize a multilevel waveform and to keep each of the PV arrays at its maximum power operating point. Experimental results carried out on a 7-level inverter are included to validate the proposed approach. Thu, 03 May 2012 18:19:57 GMT http://hdl.handle.net/2117/15776 2012-05-03T18:19:57Z Chavarría Roe, Javier; Biel Solé, Domingo; Guinjoan Gispert, Francisco; Meza Benavides, Carlos; Negroni Vera, Juan José no This paper presents an energy-balance control strategy for a cascaded single-phase grid-connected H-bridge multilevel inverter linking n independent PV arrays to the grid. The control scheme is based on an energy-sampled data model of the PV system and enables the design of a voltage loop linear discrete controller for each array ensuring the stability of the system for the whole range of PV arrays operating conditions. The control design is adapted to Phase-Shifted and Level-Shifted Carrier PWM to share the control action among the cascadeconnected bridges in order to concurrently synthesize a multilevel waveform and to keep each of the PV arrays at its maximum power operating point. Experimental results carried out on a 7-level inverter are included to validate the proposed approach. http://hdl.handle.net/2117/15713 Title: Simulation-based criteria for the power sizing of grid-connected PV systems Authors: Velasco Quesada, Guillermo; Guinjoan Gispert, Francisco; Piqué López, Robert; Román Lumbreras, Manuel; Conesa Roca, Alfons Tue, 10 Apr 2012 10:41:01 GMT http://hdl.handle.net/2117/15713 2012-04-10T10:41:01Z Velasco Quesada, Guillermo; Guinjoan Gispert, Francisco; Piqué López, Robert; Román Lumbreras, Manuel; Conesa Roca, Alfons no http://hdl.handle.net/2117/15657 Title: An ultra low-power mixed-signal back-end for passive sensor UHF RFID transponders Authors: Rodriguez, J.; Delgado Restituto, M.; Masuch, J.; Rodriguez Perez, Alberto; Alarcón Cot, Eduardo José; Rodríguez Vázquez, Ángel Abstract: This paper describes the design of mixed-signal back end for an ultrahigh-frequency sensor-enabled radio-frequency identification transponder in full compliance with the Electronic Product Code Class-1 Generation-2 protocol, defined in the standard ISO 18000-6C. The chip, implemented in a low-cost 0.35- μm CMOS technology process, includes a baseband processor, an analog-to-digital converter (ADC) to digitize the signal acquired from the external sensor, and some auxiliary circuitry for voltage regulation and reference generation. The proposed solution uses two different supply voltages, one for the processor and the other for the mixed-signal circuitry, and defines a novel communication protocol between both blocks so that analog readouts are minimally affected by the digital activity of the tag. The whole system was first functionally validated by exhaustively testing with external dc power supplies ten prototype samples, and then, the two main blocks, processor, and ADC were individually tested to assess their performance limits. Regarding the baseband processor, experiments were performed toward the calculation of its packet error rate (PER) under two typical biasing configurations of passive tags, using either crude clamps or regulators. It was found that the regulated biasing outperforms the clamping solution and obtains a PER of 3 × 10-3 with a supply voltage of 0.75 V. The current consumption of the processor during the reception and response to a Read command at maximum backward rate is only 2.2 μA from a 0.9-V supply. Regarding the ADC, it is a 10-b successive approximation register converter which obtains 9.41 b of effective resolution at 2-kS/s sampling frequency with a power consumption of 250 nW, including the dissipation of a current generation cell and the clock generation circuitry, from 1-V supply. Fri, 23 Mar 2012 19:40:41 GMT http://hdl.handle.net/2117/15657 2012-03-23T19:40:41Z Rodriguez, J.; Delgado Restituto, M.; Masuch, J.; Rodriguez Perez, Alberto; Alarcón Cot, Eduardo José; Rodríguez Vázquez, Ángel no This paper describes the design of mixed-signal back end for an ultrahigh-frequency sensor-enabled radio-frequency identification transponder in full compliance with the Electronic Product Code Class-1 Generation-2 protocol, defined in the standard ISO 18000-6C. The chip, implemented in a low-cost 0.35- μm CMOS technology process, includes a baseband processor, an analog-to-digital converter (ADC) to digitize the signal acquired from the external sensor, and some auxiliary circuitry for voltage regulation and reference generation. The proposed solution uses two different supply voltages, one for the processor and the other for the mixed-signal circuitry, and defines a novel communication protocol between both blocks so that analog readouts are minimally affected by the digital activity of the tag. The whole system was first functionally validated by exhaustively testing with external dc power supplies ten prototype samples, and then, the two main blocks, processor, and ADC were individually tested to assess their performance limits. Regarding the baseband processor, experiments were performed toward the calculation of its packet error rate (PER) under two typical biasing configurations of passive tags, using either crude clamps or regulators. It was found that the regulated biasing outperforms the clamping solution and obtains a PER of 3 × 10-3 with a supply voltage of 0.75 V. The current consumption of the processor during the reception and response to a Read command at maximum backward rate is only 2.2 μA from a 0.9-V supply. Regarding the ADC, it is a 10-b successive approximation register converter which obtains 9.41 b of effective resolution at 2-kS/s sampling frequency with a power consumption of 250 nW, including the dissipation of a current generation cell and the clock generation circuitry, from 1-V supply. http://hdl.handle.net/2117/14467 Title: N3Sim: A simulation framework for diffusion-based molecular communication Authors: Llatser Martí, Ignacio; Pascual, Iñaki; Garralda, N.; Cabellos Aparicio, Alberto; Alarcón Cot, Eduardo José Abstract: We designed N3Sim in order to simulate a set of nanomachines which communicate through molecular diffusion in a fluid medium. Wed, 11 Jan 2012 11:30:03 GMT http://hdl.handle.net/2117/14467 2012-01-11T11:30:03Z Llatser Martí, Ignacio; Pascual, Iñaki; Garralda, N.; Cabellos Aparicio, Alberto; Alarcón Cot, Eduardo José no We designed N3Sim in order to simulate a set of nanomachines which communicate through molecular diffusion in a fluid medium. http://hdl.handle.net/2117/14466 Title: A ripple-based design-oriented approach for predicting fast-scale instability in DC–DC switching power supplies Authors: Rodríguez Vilamitjana, Enric; El Aroudi, Abdelali; Guinjoan Gispert, Francisco; Alarcón Cot, Eduardo José Abstract: This paper presents a design-oriented analytical approach for predicting fast-scale instability in power electronics converters under voltage-mode control strategy. This approach is based on the use of the ripple amplitude of the feedback control voltage as an index for predicting subharmonic oscillations in these systems. First, the work revisits the stability analysis technique based on the nonlinear discrete-time model, demonstrating that the ripple amplitude can be included within the expression of the Jacobian matrix of this model, hence giving a mathematical support to extend the ripple index to more complex topologies. A simple but representative buck converter under voltage-mode control is used to illustrate the approach. Using the ripple-based index, closed-form expressions of stability boundaries are derived. Unlike other available results obtained from existing methods, the stability boundary, in this work is expressed analytically in terms of both power stage and controller design parameters. Moreover, one can determine how these parameters are involved in the closed form expressions and, furthermore, how each parameter affects the stability of the system. The approach is validated by numerical simulations from the state equations and also experimentally within a wide range of the design parameter space. Wed, 11 Jan 2012 11:10:08 GMT http://hdl.handle.net/2117/14466 2012-01-11T11:10:08Z Rodríguez Vilamitjana, Enric; El Aroudi, Abdelali; Guinjoan Gispert, Francisco; Alarcón Cot, Eduardo José no This paper presents a design-oriented analytical approach for predicting fast-scale instability in power electronics converters under voltage-mode control strategy. This approach is based on the use of the ripple amplitude of the feedback control voltage as an index for predicting subharmonic oscillations in these systems. First, the work revisits the stability analysis technique based on the nonlinear discrete-time model, demonstrating that the ripple amplitude can be included within the expression of the Jacobian matrix of this model, hence giving a mathematical support to extend the ripple index to more complex topologies. A simple but representative buck converter under voltage-mode control is used to illustrate the approach. Using the ripple-based index, closed-form expressions of stability boundaries are derived. Unlike other available results obtained from existing methods, the stability boundary, in this work is expressed analytically in terms of both power stage and controller design parameters. Moreover, one can determine how these parameters are involved in the closed form expressions and, furthermore, how each parameter affects the stability of the system. The approach is validated by numerical simulations from the state equations and also experimentally within a wide range of the design parameter space. http://hdl.handle.net/2117/13229 Title: Modeling of switching frequency instabilities in buck-based DC-AC H-bridge inverters Authors: El Aroudi, Abdelali; Rodríguez Vilamitjana, Enric; Orabi, Mohamed; Alarcón Cot, Eduardo José Abstract: In this paper, the dynamical behavior of a full bridge DC–AC buck inverter controlled by fixed frequency and PWM is studied. After showing that the system can undergo both period-doubling and Neimark–Sacker bifurcation at the fast scale (switching period) by using the exact switching model, an exact solution discrete-time model able to predict both instability phenomena is derived. The model is obtained without making the quasi-static approximation and it can be used to obtain the useful operation region in the multi-dimensional design parameter space from time domain simulations in a very fast and accurate manner. Based on the study of the system, some design guidelines are provided. Mon, 19 Sep 2011 09:11:39 GMT http://hdl.handle.net/2117/13229 2011-09-19T09:11:39Z El Aroudi, Abdelali; Rodríguez Vilamitjana, Enric; Orabi, Mohamed; Alarcón Cot, Eduardo José no In this paper, the dynamical behavior of a full bridge DC–AC buck inverter controlled by fixed frequency and PWM is studied. After showing that the system can undergo both period-doubling and Neimark–Sacker bifurcation at the fast scale (switching period) by using the exact switching model, an exact solution discrete-time model able to predict both instability phenomena is derived. The model is obtained without making the quasi-static approximation and it can be used to obtain the useful operation region in the multi-dimensional design parameter space from time domain simulations in a very fast and accurate manner. Based on the study of the system, some design guidelines are provided. http://hdl.handle.net/2117/9501 Title: Soft-limiter circuit forms basis of simple AM modulator Authors: Martínez García, Herminio; García, Encarna; Gámiz Caro, Juan Thu, 07 Oct 2010 08:53:20 GMT http://hdl.handle.net/2117/9501 2010-10-07T08:53:20Z Martínez García, Herminio; García, Encarna; Gámiz Caro, Juan no http://hdl.handle.net/2117/9462 Title: Mismatch and dynamic modeling of current sources in current-steering cmos d/a converters: an extended design procedure Authors: Albiol, Miquel; González Jiménez, José Luis; Alarcón Cot, Eduardo José Abstract: This paper presents an improved modeling of the effect of random mismatch and current source transient switching behavior on the performance of current-steering CMOS digital-toanalog converters (DACs). The work considers two current source cell topologies, namely a simple cell and a cascoded cell, obtaining the relation of transistors design parameters to the static and dynamic models. On the one hand, a mismatching statistical analysis is applied to all the transistors of the current source circuit, which allows to define design expressions relating the circuit parameters to the DAC specifications without the need of arbitrary design margins or Monte Carlo simulations. On the other hand, improved analysis of the current source switching characteristics provides a more realistic modeling of the relation between transistors sizes and output current settling time. By including these two improved models into the usual design procedure, circuit sizing for optimum settling time and proper static behavior can be obtained analytically, reverting in smaller current source area, and, hence, in an overall DAC area reduction. Wed, 06 Oct 2010 13:42:24 GMT http://hdl.handle.net/2117/9462 2010-10-06T13:42:24Z Albiol, Miquel; González Jiménez, José Luis; Alarcón Cot, Eduardo José no This paper presents an improved modeling of the effect of random mismatch and current source transient switching behavior on the performance of current-steering CMOS digital-toanalog converters (DACs). The work considers two current source cell topologies, namely a simple cell and a cascoded cell, obtaining the relation of transistors design parameters to the static and dynamic models. On the one hand, a mismatching statistical analysis is applied to all the transistors of the current source circuit, which allows to define design expressions relating the circuit parameters to the DAC specifications without the need of arbitrary design margins or Monte Carlo simulations. On the other hand, improved analysis of the current source switching characteristics provides a more realistic modeling of the relation between transistors sizes and output current settling time. By including these two improved models into the usual design procedure, circuit sizing for optimum settling time and proper static behavior can be obtained analytically, reverting in smaller current source area, and, hence, in an overall DAC area reduction. http://hdl.handle.net/2117/9441 Title: Audio equalizer features transimpedance Q-enhancement topology Authors: Martínez García, Herminio; García, Encarna; Vidal López, Eva María Wed, 06 Oct 2010 11:22:40 GMT http://hdl.handle.net/2117/9441 2010-10-06T11:22:40Z Martínez García, Herminio; García, Encarna; Vidal López, Eva María no http://hdl.handle.net/2117/9438 Title: Soft limiter for oscillator circuits uses emitter-degenerated differential pair Authors: Martínez García, Herminio; García, Encarna Wed, 06 Oct 2010 11:12:37 GMT http://hdl.handle.net/2117/9438 2010-10-06T11:12:37Z Martínez García, Herminio; García, Encarna no