http://hdl.handle.net/2117/3126 Thu, 20 Jun 2013 06:55:42 GMT 2013-06-20T06:55:42Z webmaster.bupc@upc.edu Universitat Politècnica de Catalunya. Servei de Biblioteques i Documentació no http://hdl.handle.net/2117/19516 Title: Evaluación formativa usando exámenes no presenciales Authors: López Álvarez, David; Sánchez Carracedo, Fermín; Cruz Díaz, Josep Llorenç; Fernández Jiménez, Agustín Abstract: Los exámenes tradicionales están orientados a la evaluación sumativa, no a la formativa, y provocan un aprendizaje superficial, más que un aprendizaje profundo. Su objetivo es evaluar, no facilitar el aprendizaje. Los estudiantes perciben que su futuro a corto plazo depende de su nota en un examen, por lo que orientan su estudio a aprobar dicho examen. En este artículo se exponen las ventajas e inconvenientes de realizar un examen no presencial, con evaluación sumativa y formativa, que los estudiantes realizan fuera de clase a lo largo de un periodo de tiempo mucho más largo que el de un examen tradicional, lo que les ayuda a conseguir un aprendizaje profundo. Traditional exams are focused on the summative assessment, not on the formative one. Its aim is to evaluate, not to facilitate learning, so it results in superficial learning rather than deep learning. Thus, students perceive that their short-term future depends on their note in the exam, so their study is guided to pass the examination. In this paper we propose a take-home exam in which students have more time to solve the questions and are not restricted by the sources they can consult, thereby providing a highly educational task in which students experience a deep learning process. Wed, 05 Jun 2013 09:50:29 GMT http://hdl.handle.net/2117/19516 2013-06-05T09:50:29Z López Álvarez, David; Sánchez Carracedo, Fermín; Cruz Díaz, Josep Llorenç; Fernández Jiménez, Agustín no Modelos de evaluación, Evaluación formativa, Evaluación sumativa, Evaluación de competencias, Modelos de aprendizaje Los exámenes tradicionales están orientados a la evaluación sumativa, no a la formativa, y provocan un aprendizaje superficial, más que un aprendizaje profundo. Su objetivo es evaluar, no facilitar el aprendizaje. Los estudiantes perciben que su futuro a corto plazo depende de su nota en un examen, por lo que orientan su estudio a aprobar dicho examen. En este artículo se exponen las ventajas e inconvenientes de realizar un examen no presencial, con evaluación sumativa y formativa, que los estudiantes realizan fuera de clase a lo largo de un periodo de tiempo mucho más largo que el de un examen tradicional, lo que les ayuda a conseguir un aprendizaje profundo. Traditional exams are focused on the summative assessment, not on the formative one. Its aim is to evaluate, not to facilitate learning, so it results in superficial learning rather than deep learning. Thus, students perceive that their short-term future depends on their note in the exam, so their study is guided to pass the examination. In this paper we propose a take-home exam in which students have more time to solve the questions and are not restricted by the sources they can consult, thereby providing a highly educational task in which students experience a deep learning process. http://hdl.handle.net/2117/19512 Title: Systematic energy characterization of CMP/SMT processor systems via automated micro-benchmarks Authors: Bertrán, Ramon; Buyuktosunoglu, Alper; Gupta, Meeta S.; González Tallada, Marc; Bose, Pradip Abstract: Microprocessor-based systems today are composed of multi-core, multi-threaded processors with complex cache hierarchies and gigabytes of main memory. Accurate characterization of such a system, through predictive pre-silicon modeling and/or diagnostic postsilicon measurement based analysis are increasingly cumbersome and error prone. This is especially true of energy-related characterization studies. In this paper, we take the position that automated micro-benchmarks generated with particular objectives in mind hold the key to obtaining accurate energy-related characterization. As such, we first present a flexible micro-benchmark generation framework (MicroProbe) that is used to probe complex multi-core/multi-threaded systems with a variety and range of energy-related queries in mind. We then present experimental results centered around an IBM POWER7 CMP/SMT system to demonstrate how the systematically generated micro-benchmarks can be used to answer three specific queries: (a) How to project application-specific (and if needed, phase-specific) power consumption with component-wise breakdowns? (b) How to measure energy-per-instruction (EPI) values for the target machine? (c) How to bound the worst-case (maximum) power consumption in order to determine safe, but practical (i.e. affordable) packaging or cooling solutions? The solution approaches to the above problems are all new. Hardware measurement based analysis shows superior power projection accuracy (with error margins of less than 2.3% across SPEC CPU2006) as well as max-power stressing capability (with 10.7% increase in processor power over the very worst-case power seen during the execution of SPEC CPU2006 applications). Wed, 05 Jun 2013 07:39:22 GMT http://hdl.handle.net/2117/19512 2013-06-05T07:39:22Z Bertrán, Ramon; Buyuktosunoglu, Alper; Gupta, Meeta S.; González Tallada, Marc; Bose, Pradip no Microprocessor chips, Multi-threading, Multiprocessing systems Microprocessor-based systems today are composed of multi-core, multi-threaded processors with complex cache hierarchies and gigabytes of main memory. Accurate characterization of such a system, through predictive pre-silicon modeling and/or diagnostic postsilicon measurement based analysis are increasingly cumbersome and error prone. This is especially true of energy-related characterization studies. In this paper, we take the position that automated micro-benchmarks generated with particular objectives in mind hold the key to obtaining accurate energy-related characterization. As such, we first present a flexible micro-benchmark generation framework (MicroProbe) that is used to probe complex multi-core/multi-threaded systems with a variety and range of energy-related queries in mind. We then present experimental results centered around an IBM POWER7 CMP/SMT system to demonstrate how the systematically generated micro-benchmarks can be used to answer three specific queries: (a) How to project application-specific (and if needed, phase-specific) power consumption with component-wise breakdowns? (b) How to measure energy-per-instruction (EPI) values for the target machine? (c) How to bound the worst-case (maximum) power consumption in order to determine safe, but practical (i.e. affordable) packaging or cooling solutions? The solution approaches to the above problems are all new. Hardware measurement based analysis shows superior power projection accuracy (with error margins of less than 2.3% across SPEC CPU2006) as well as max-power stressing capability (with 10.7% increase in processor power over the very worst-case power seen during the execution of SPEC CPU2006 applications). http://hdl.handle.net/2117/19470 Title: Automatic I/O scheduler selection through online workload analysis Authors: Nou Castell, Ramon; Giralt, Jacobo; Cortés Rosselló, Antonio Abstract: I/O performance is a bottleneck for many workloads. The I/O scheduler plays an important role in it. It is typically configured once by the administrator and there is no selection that suits the system at every time. Every I/O scheduler has a different behavior depending on the workload and the device. We present a method to select automatically the most suitable I/O scheduler for the ongoing workload. This selection is done online, using a workload analysis method with small I/O traces, finding common I/O patterns. Our dynamic mechanism adapts automatically to one of the best schedulers, sometimes achieving improvements on I/O performance for heterogeneous workloads beyond those of any fixed configuration (up to 5%). This technique works with any application and device type (RAID, HDD, SSD), as long as we have a system parameter to tune. It does not need disk simulations or hardware models, which are normally unavailable. We evaluate it in different setups, and with different benchmarks. Fri, 31 May 2013 09:33:22 GMT http://hdl.handle.net/2117/19470 2013-05-31T09:33:22Z Nou Castell, Ramon; Giralt, Jacobo; Cortés Rosselló, Antonio no I/O scheduling, Pattern matching, Optimization I/O performance is a bottleneck for many workloads. The I/O scheduler plays an important role in it. It is typically configured once by the administrator and there is no selection that suits the system at every time. Every I/O scheduler has a different behavior depending on the workload and the device. We present a method to select automatically the most suitable I/O scheduler for the ongoing workload. This selection is done online, using a workload analysis method with small I/O traces, finding common I/O patterns. Our dynamic mechanism adapts automatically to one of the best schedulers, sometimes achieving improvements on I/O performance for heterogeneous workloads beyond those of any fixed configuration (up to 5%). This technique works with any application and device type (RAID, HDD, SSD), as long as we have a system parameter to tune. It does not need disk simulations or hardware models, which are normally unavailable. We evaluate it in different setups, and with different benchmarks. http://hdl.handle.net/2117/19425 Title: Symmetric rank-k update on clusters of multicore processors with SMPSs Authors: Badia Sala, Rosa Maria; Labarta Mancho, Jesús José; Marjanovic, Vladimir; Martín Huertas, Alberto Francisco; Mayo, Rafael; Quintana-Ortí, Enrique Salvador; Reyes, Ruymán Abstract: We investigate the use of the SMPSs programming model to leverage task parallelism in the execution of a message-pas sing implementation of the symmetric rank- k update on clusters equipped with multicore processors. Our experience shows that the major difficulties to adapt the code to the MPI/SMPSs instance of this programming model are due to the usage of the conventional column-major layout of matrices in numerical libraries. On the other hand, the experimental results show a considerable increase in the performance and scalability of our solution when compared with the standard options based on the use of a pure MPI approach or a hybrid one that combines MPI/multi-threaded BLAS. Tue, 28 May 2013 09:48:52 GMT http://hdl.handle.net/2117/19425 2013-05-28T09:48:52Z Badia Sala, Rosa Maria; Labarta Mancho, Jesús José; Marjanovic, Vladimir; Martín Huertas, Alberto Francisco; Mayo, Rafael; Quintana-Ortí, Enrique Salvador; Reyes, Ruymán no Linear algebra, ScaLAPACK, Clusters of multi-core processors, SMPSs, Message passing numerical libraries We investigate the use of the SMPSs programming model to leverage task parallelism in the execution of a message-pas sing implementation of the symmetric rank- k update on clusters equipped with multicore processors. Our experience shows that the major difficulties to adapt the code to the MPI/SMPSs instance of this programming model are due to the usage of the conventional column-major layout of matrices in numerical libraries. On the other hand, the experimental results show a considerable increase in the performance and scalability of our solution when compared with the standard options based on the use of a pure MPI approach or a hybrid one that combines MPI/multi-threaded BLAS. http://hdl.handle.net/2117/19424 Title: Analyzing long-term access locality to find ways to improve distributed storage systems Authors: Miranda Bueno, Alberto; Cortés Rosselló, Antonio Abstract: An efficient design for a distributed filesystem originates from a deep understanding of common access patterns and user behavior which is obtained through a deep analysis of traces and snapshots. In this paper we analyze traces for eight distributed filesystems that represent a mix of workloads taken from educational, research and commercial environments. We focused on characterizing block access patterns, amount of block sharing and working set size over long periods of time, and we tried to find common behaviors for all workloads that can be generalized to other storage systems. We found that most environments shared large amounts of blocks over time, and that block sharing was significantly affected by repetitive human behavior. We also found that block lifetimes tended to be short, but there were significant amounts of blocks with long lifetimes that were accessed over many consecutive days. Lastly, we determined that most daily accesses were made to a reduced set of blocks. We strongly believe that these findings can be used to improve long-term caching policies as well as data placement algorithms, thus increasing the performance of distributed storage systems. Tue, 28 May 2013 09:15:54 GMT http://hdl.handle.net/2117/19424 2013-05-28T09:15:54Z Miranda Bueno, Alberto; Cortés Rosselló, Antonio no An efficient design for a distributed filesystem originates from a deep understanding of common access patterns and user behavior which is obtained through a deep analysis of traces and snapshots. In this paper we analyze traces for eight distributed filesystems that represent a mix of workloads taken from educational, research and commercial environments. We focused on characterizing block access patterns, amount of block sharing and working set size over long periods of time, and we tried to find common behaviors for all workloads that can be generalized to other storage systems. We found that most environments shared large amounts of blocks over time, and that block sharing was significantly affected by repetitive human behavior. We also found that block lifetimes tended to be short, but there were significant amounts of blocks with long lifetimes that were accessed over many consecutive days. Lastly, we determined that most daily accesses were made to a reduced set of blocks. We strongly believe that these findings can be used to improve long-term caching policies as well as data placement algorithms, thus increasing the performance of distributed storage systems. http://hdl.handle.net/2117/19370 Title: Empowering automatic data-center management with machine learning Authors: Berral García, Josep Lluís; Gavaldà Mestre, Ricard; Torres Viñals, Jordi Abstract: The Cloud as computing paradigm has become nowadays crucial for most Internet business models. Managing and optimizing its performance on a moment-by-moment basis is not easy given as the amount and diversity of elements involved (hardware, applications, workloads, customer needs...). Here we show how a combination of scheduling algorithms and data mining techniques helps improving the performance and profitability of a data-center running virtualized web-services. We model the data-center's main resources (CPU, memory, IO), quality of service (viewed as response time), and workloads (incoming streams of requests) from past executions. We show how these models to help scheduling algorithms make better decisions about job and resource allocation, aiming for a balance between throughput, quality of service, and power consumption. Wed, 22 May 2013 11:19:56 GMT http://hdl.handle.net/2117/19370 2013-05-22T11:19:56Z Berral García, Josep Lluís; Gavaldà Mestre, Ricard; Torres Viñals, Jordi no The Cloud as computing paradigm has become nowadays crucial for most Internet business models. Managing and optimizing its performance on a moment-by-moment basis is not easy given as the amount and diversity of elements involved (hardware, applications, workloads, customer needs...). Here we show how a combination of scheduling algorithms and data mining techniques helps improving the performance and profitability of a data-center running virtualized web-services. We model the data-center's main resources (CPU, memory, IO), quality of service (viewed as response time), and workloads (incoming streams of requests) from past executions. We show how these models to help scheduling algorithms make better decisions about job and resource allocation, aiming for a balance between throughput, quality of service, and power consumption. http://hdl.handle.net/2117/19366 Title: IT or not to be: the impact of Moodle in the education of developing countries Authors: García Almiñana, Jordi; Somé, Michel; Ayguadé Parra, Eduard; Cabré Garcia, José M.; Casany Guerrero, María José; Frigola Bourlon, Manel; Galanis, Nikolaos; García-Cervigon Gutiérrez, Manuel; Guerrero Zapata, Manel; Muñoz Gracia, María del Pilar Abstract: E-learning environments, such as Moodle, provide a technology that fosters the improvement of the educational system in developed countries, where education is traditionally performed with relatively high standards of quality. A large number of case studies and research have been conducted to demonstrate how e-learning technologies can be applied to improve both training and learning processes. However, these technologies have not been proved efficient when applied to developing countries. The challenges that must be addressed in developing countries, both technological and societal, are much more complex and the possible solution margins are more constrained than those existing in the context where these technologies have been created. In this paper we show how Moodle can be used to improve the quality of education in developing countries and, even more important, how can be used to turn the educational system more sustainable and effective in the long-term. We describe our experience in implementing a programming course in Moodle for the Higher School of Informatics at the Université Polytechnique de Bobo-Dioulasso, in Burkina Faso (West Africa), joining efforts with local professors in designing and implementing the learning system. The case example has been designed having in mind a number of contextual problems: lack of lecturers, excessive teaching hours per lecturer, massive classes, and curricula organization and stability, among others. We finally discuss how the teaching effort is reduced, the students’ knowledge and capacity improves, and the institutional academic model can be guaranteed with the proposal. For this reason, we claim that information technologies in developing countries are a cost-effective way to guarantee the objectives originally defined in the academic curricula and, therefore, deal with the problem of the education. Wed, 22 May 2013 07:16:25 GMT http://hdl.handle.net/2117/19366 2013-05-22T07:16:25Z García Almiñana, Jordi; Somé, Michel; Ayguadé Parra, Eduard; Cabré Garcia, José M.; Casany Guerrero, María José; Frigola Bourlon, Manel; Galanis, Nikolaos; García-Cervigon Gutiérrez, Manuel; Guerrero Zapata, Manel; Muñoz Gracia, María del Pilar no Moodle, e-Learning, Education in developing countries, Programming course E-learning environments, such as Moodle, provide a technology that fosters the improvement of the educational system in developed countries, where education is traditionally performed with relatively high standards of quality. A large number of case studies and research have been conducted to demonstrate how e-learning technologies can be applied to improve both training and learning processes. However, these technologies have not been proved efficient when applied to developing countries. The challenges that must be addressed in developing countries, both technological and societal, are much more complex and the possible solution margins are more constrained than those existing in the context where these technologies have been created. In this paper we show how Moodle can be used to improve the quality of education in developing countries and, even more important, how can be used to turn the educational system more sustainable and effective in the long-term. We describe our experience in implementing a programming course in Moodle for the Higher School of Informatics at the Université Polytechnique de Bobo-Dioulasso, in Burkina Faso (West Africa), joining efforts with local professors in designing and implementing the learning system. The case example has been designed having in mind a number of contextual problems: lack of lecturers, excessive teaching hours per lecturer, massive classes, and curricula organization and stability, among others. We finally discuss how the teaching effort is reduced, the students’ knowledge and capacity improves, and the institutional academic model can be guaranteed with the proposal. For this reason, we claim that information technologies in developing countries are a cost-effective way to guarantee the objectives originally defined in the academic curricula and, therefore, deal with the problem of the education. http://hdl.handle.net/2117/19282 Title: Supporting stateful tasks in a dataflow graph Authors: Gajinov, Vladimir; Stipic, Srdjan; Unsal, Osman Sabri; Harris, Tim; Ayguadé Parra, Eduard; Cristal Kestelman, Adrián Abstract: This paper introduces Atomic Dataflow Model (ADF) - a programming model for shared-memory systems that combines aspects of dataflow programming with the use of explicitly mutable state. The model provides language constructs that allow a programmer to delineate a program into a set of tasks and to explicitly define input data for each task. This information is conveyed to the ADF runtime system which constructs the task dependency graph and builds the necessary infrastructure for dataflow execution. However, the key aspect of the proposed model is that it does not require the programmer to specify all of the task’s dependencies exp licitly, but only those that imply logical ordering between tasks. The ADF model manages the remainder of inter-task dependencies automatically, by executing the body of the task within an implicit memory transaction. This provides an easy- to -program optimistic concurrency substrate and enables a task to safely share data with other concurrent tasks. In this paper, we describe the ADF model and show how it can increase the programmability of shared memory systems. Thu, 16 May 2013 10:26:49 GMT http://hdl.handle.net/2117/19282 2013-05-16T10:26:49Z Gajinov, Vladimir; Stipic, Srdjan; Unsal, Osman Sabri; Harris, Tim; Ayguadé Parra, Eduard; Cristal Kestelman, Adrián no Dataflow, Parallelization, Transactional memory This paper introduces Atomic Dataflow Model (ADF) - a programming model for shared-memory systems that combines aspects of dataflow programming with the use of explicitly mutable state. The model provides language constructs that allow a programmer to delineate a program into a set of tasks and to explicitly define input data for each task. This information is conveyed to the ADF runtime system which constructs the task dependency graph and builds the necessary infrastructure for dataflow execution. However, the key aspect of the proposed model is that it does not require the programmer to specify all of the task’s dependencies exp licitly, but only those that imply logical ordering between tasks. The ADF model manages the remainder of inter-task dependencies automatically, by executing the body of the task within an implicit memory transaction. This provides an easy- to -program optimistic concurrency substrate and enables a task to safely share data with other concurrent tasks. In this paper, we describe the ADF model and show how it can increase the programmability of shared memory systems. http://hdl.handle.net/2117/19279 Title: Transactional access to shared memory in StarSs, a task based programming model Authors: Gayatri, Rahulkumar; Badia Sala, Rosa Maria; Ayguadé Parra, Eduard; Lujan, M; Watson, I. Abstract: With an increase in the number of processors on a single chip, programming environments which facilitate the exploitation of par- allelism on multicore architectures have become a necessity. StarSs is a task-based programming model that enables a flexible and high level programming. Although task synchronization in StarSs is based on data flow and dependency analysis, some applications (e.g. reductions )require locks to access shared data. Transactional Memory is an alternative to lock-based synchronization for controlling access to shared data. In this paper we explore the idea of integrating a lightweight Software Transactional Memory (STM) library, TinySTM , into an implementation of StarSs (SMPSs). The SMPSs run- time and the compiler have been modified to include and use calls to the STM library. We evaluated this approach on four applications and observe better performance in applications with high lock contention. Thu, 16 May 2013 09:52:14 GMT http://hdl.handle.net/2117/19279 2013-05-16T09:52:14Z Gayatri, Rahulkumar; Badia Sala, Rosa Maria; Ayguadé Parra, Eduard; Lujan, M; Watson, I. no Data flow, Dependency analysis, High-level programming, Lock-based synchronization, Multicore architectures, Programming environment, Programming models, Runtimes, Shared data, Shared memories, Single chips, Software transactional memory, STM Library, Task synchronization, Task-based, Transactional memory With an increase in the number of processors on a single chip, programming environments which facilitate the exploitation of par- allelism on multicore architectures have become a necessity. StarSs is a task-based programming model that enables a flexible and high level programming. Although task synchronization in StarSs is based on data flow and dependency analysis, some applications (e.g. reductions )require locks to access shared data. Transactional Memory is an alternative to lock-based synchronization for controlling access to shared data. In this paper we explore the idea of integrating a lightweight Software Transactional Memory (STM) library, TinySTM , into an implementation of StarSs (SMPSs). The SMPSs run- time and the compiler have been modified to include and use calls to the STM library. We evaluated this approach on four applications and observe better performance in applications with high lock contention. http://hdl.handle.net/2117/19276 Title: Vector extensions for decision support DBMS acceleration Authors: Hayes, Timothy; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo Abstract: Database management systems (DBMS) have become an essential tool for industry and research and are often a significant component of data centres. As a result of this criticality, efficient execution of DBMS engines has become an important area of investigation. This work takes a top-down approach to accelerating decision support systems (DSS) on x86-64 microprocessors using vector ISA exten- sions. In the first step, a leading DSS DBMS is analysed for potential data-level parallelism. We discuss why the existing multimedia SIMD extensions (SSE/AVX) are not suitable for capturing this parallelism and propose a complementary instruction set reminiscent of classical vector architectures. The instruction set is implemented using unin- trusive modifications to a modern x86-64 microarchitecture tailored for DSS DBMS. The ISA and microarchitecture are evaluated using a cycle-accurate x86-64 microarchitectural simulator coupled with a highly-detailed memory simulator. We have found a single oper- ator is responsible for 41% of total execution time for the TPC-H DSS benchmark. Our results show performance speedups between 1.94x and 4.56x for an implementation of this operator run with our proposed hardware modifications. Thu, 16 May 2013 09:15:37 GMT http://hdl.handle.net/2117/19276 2013-05-16T09:15:37Z Hayes, Timothy; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo no Database management systems (DBMS) have become an essential tool for industry and research and are often a significant component of data centres. As a result of this criticality, efficient execution of DBMS engines has become an important area of investigation. This work takes a top-down approach to accelerating decision support systems (DSS) on x86-64 microprocessors using vector ISA exten- sions. In the first step, a leading DSS DBMS is analysed for potential data-level parallelism. We discuss why the existing multimedia SIMD extensions (SSE/AVX) are not suitable for capturing this parallelism and propose a complementary instruction set reminiscent of classical vector architectures. The instruction set is implemented using unin- trusive modifications to a modern x86-64 microarchitecture tailored for DSS DBMS. The ISA and microarchitecture are evaluated using a cycle-accurate x86-64 microarchitectural simulator coupled with a highly-detailed memory simulator. We have found a single oper- ator is responsible for 41% of total execution time for the TPC-H DSS benchmark. Our results show performance speedups between 1.94x and 4.56x for an implementation of this operator run with our proposed hardware modifications. http://hdl.handle.net/2117/19275 Title: Automatic refinement of parallel applications structure detection Authors: González, Juan; Huck, Kevin; Giménez Lucas, Judit; Labarta Mancho, Jesús José Abstract: Analyzing parallel programs has become increasingly difficult due to the immense amount of information collected on large systems. In this scenario, cluster analysis has been proved to be a useful technique to reduce the amount of data to analyze. A good example is the use of the density-based cluster algorithm DBSCAN to identify similar single program multiple data (SPMD) computing phases in message-passing applications. This structure detection simplifies the analyst work as the whole information available is reduced to a small set of clusters. However, DBSCAN presents two major problems: it is very sensitive to its parametrization and is not capable of correctly detect clusters when the data set has different densities across the data space. In this paper, we introduce the Aggregative Cluster Refinement, an iterative algorithm that produces more accurate structure detections of SPMD phases than DBSCAN. In addition, it is able to detect clusters with different densities Thu, 16 May 2013 08:57:41 GMT http://hdl.handle.net/2117/19275 2013-05-16T08:57:41Z González, Juan; Huck, Kevin; Giménez Lucas, Judit; Labarta Mancho, Jesús José no Analyzing parallel programs has become increasingly difficult due to the immense amount of information collected on large systems. In this scenario, cluster analysis has been proved to be a useful technique to reduce the amount of data to analyze. A good example is the use of the density-based cluster algorithm DBSCAN to identify similar single program multiple data (SPMD) computing phases in message-passing applications. This structure detection simplifies the analyst work as the whole information available is reduced to a small set of clusters. However, DBSCAN presents two major problems: it is very sensitive to its parametrization and is not capable of correctly detect clusters when the data set has different densities across the data space. In this paper, we introduce the Aggregative Cluster Refinement, an iterative algorithm that produces more accurate structure detections of SPMD phases than DBSCAN. In addition, it is able to detect clusters with different densities http://hdl.handle.net/2117/18559 Title: Integrating dataflow abstractions into the shared memory model Authors: Gajinov, Vladimir; Stipic, Srdjan; Unsal, Osman Sabri; Harris, Tim; Ayguadé Parra, Eduard; Cristal Kestelman, Adrián Abstract: In this paper we present Atomic Dataflow model (ADF), a new task-based parallel programming model for C/C++ which integrates dataflow abstractions into the shared memory programming model. The ADF model provides pragma directives that allow a programmer to organize a program into a set of tasks and to explicitly define input data for each task. The task dependency information is conveyed to the ADF runtime system which constructs the dataflow task graph and builds the necessary infrastructure for dataflow execution. Additionally, the ADF model allows tasks to share data. The key idea is that comput ation is triggered by dataflow between tasks but that, within a task, execution occurs by making atomic updates to common mutable state. To that end, the ADF model employs transactional memory which guarantees atomicity of shared memory updates. We show examples that illustrate how the programmability of shared memory can be improved using the ADF model. Moreover, our evaluation shows that the ADF model performs well in comparison with programs para llelized using OpenMP and transactional memory. Wed, 03 Apr 2013 10:24:08 GMT http://hdl.handle.net/2117/18559 2013-04-03T10:24:08Z Gajinov, Vladimir; Stipic, Srdjan; Unsal, Osman Sabri; Harris, Tim; Ayguadé Parra, Eduard; Cristal Kestelman, Adrián no In this paper we present Atomic Dataflow model (ADF), a new task-based parallel programming model for C/C++ which integrates dataflow abstractions into the shared memory programming model. The ADF model provides pragma directives that allow a programmer to organize a program into a set of tasks and to explicitly define input data for each task. The task dependency information is conveyed to the ADF runtime system which constructs the dataflow task graph and builds the necessary infrastructure for dataflow execution. Additionally, the ADF model allows tasks to share data. The key idea is that comput ation is triggered by dataflow between tasks but that, within a task, execution occurs by making atomic updates to common mutable state. To that end, the ADF model employs transactional memory which guarantees atomicity of shared memory updates. We show examples that illustrate how the programmability of shared memory can be improved using the ADF model. Moreover, our evaluation shows that the ADF model performs well in comparison with programs para llelized using OpenMP and transactional memory. http://hdl.handle.net/2117/18558 Title: On the instrumentation of OpenMP and OmpSs Tasking constructs Authors: Servat, Harald; Teruel, Xavier; Llort Sanchez, German; Duran, Alejandro; Giménez, J.; Martorell Bofill, Xavier; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José Abstract: Parallelism has become more and more commonplace with the advent of the multicore processors. Although different parallel pro- gramming models have arisen to exploit the computing capabilities of such processors, developing applications that take benefit of these pro- cessors may not be easy. And what is worse, the performance achieved by the parallel version of the application may not be what the developer expected, as a result of a dubious ut ilization of the resources offered by the processor. We present in this paper a fruitful synergy of a shared memory parallel compiler and runtime, and a performance extraction library. The objective of this work is not only to reduce the performance analysis life-cycle when doing the parallelization of an application, but also to extend the analysis experience of the parallel application by incorporating data that is only known in the compiler and runtime side. Additionally we present performance results obtained with the execution of instrumented application and evaluate the overhead of the instrumentation. Wed, 03 Apr 2013 10:14:57 GMT http://hdl.handle.net/2117/18558 2013-04-03T10:14:57Z Servat, Harald; Teruel, Xavier; Llort Sanchez, German; Duran, Alejandro; Giménez, J.; Martorell Bofill, Xavier; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José no Parallelism has become more and more commonplace with the advent of the multicore processors. Although different parallel pro- gramming models have arisen to exploit the computing capabilities of such processors, developing applications that take benefit of these pro- cessors may not be easy. And what is worse, the performance achieved by the parallel version of the application may not be what the developer expected, as a result of a dubious ut ilization of the resources offered by the processor. We present in this paper a fruitful synergy of a shared memory parallel compiler and runtime, and a performance extraction library. The objective of this work is not only to reduce the performance analysis life-cycle when doing the parallelization of an application, but also to extend the analysis experience of the parallel application by incorporating data that is only known in the compiler and runtime side. Additionally we present performance results obtained with the execution of instrumented application and evaluate the overhead of the instrumentation. http://hdl.handle.net/2117/18498 Title: Accelerating boosting-based face detection on GPUs Authors: Oro, David; Fernández, Carles; Segura, Carlos; Martorell Bofill, Xavier; Hernando Pericás, Francisco Javier Abstract: The goal of face detection is to determine the presence of faces in arbitrary images, along with their locations and dimensions. As it happens with any graphics workloads, these algorithms benefit from data-level parallelism. Existing parallelization efforts strictly focus on mapping different di- vide and conquer strategies into multicore CPUs and GPUs. However, even the most advanced single-chip many-core pro- cessors to date are still struggling to effectively handle real- time face detection under high-definition video workloads. To address this challenge, face detection algorithms typically avoid computations by dynamically evaluating a boosted cascade of classifiers. Unfortunately, this technique yields a low ALU occupancy in architectures such as GPUs, which heavily rely on large SIMD widths for maximizing data-level parallelism. In this paper we present several techniques to increase the performance of the cascade evaluation kernel, which is the most resource-intensive part of the face detection pipeline. Particularly, the usage of concurrent kernel execution in combination with cascades generated with the GentleBoost algorithm solves the problem of GPU underutilization, and achieves a 5X speedup in 1080p videos on average over the fastest known implementations, while slightly improving the accuracy. Finally, we also studied the parallelization of the cascade training process and its scalability under SMP platforms. The proposed parallelization strategy exploits both task and data-level parallelism and achieves a 3.5X speedup over single-threaded implementations Fri, 22 Mar 2013 13:12:26 GMT http://hdl.handle.net/2117/18498 2013-03-22T13:12:26Z Oro, David; Fernández, Carles; Segura, Carlos; Martorell Bofill, Xavier; Hernando Pericás, Francisco Javier no The goal of face detection is to determine the presence of faces in arbitrary images, along with their locations and dimensions. As it happens with any graphics workloads, these algorithms benefit from data-level parallelism. Existing parallelization efforts strictly focus on mapping different di- vide and conquer strategies into multicore CPUs and GPUs. However, even the most advanced single-chip many-core pro- cessors to date are still struggling to effectively handle real- time face detection under high-definition video workloads. To address this challenge, face detection algorithms typically avoid computations by dynamically evaluating a boosted cascade of classifiers. Unfortunately, this technique yields a low ALU occupancy in architectures such as GPUs, which heavily rely on large SIMD widths for maximizing data-level parallelism. In this paper we present several techniques to increase the performance of the cascade evaluation kernel, which is the most resource-intensive part of the face detection pipeline. Particularly, the usage of concurrent kernel execution in combination with cascades generated with the GentleBoost algorithm solves the problem of GPU underutilization, and achieves a 5X speedup in 1080p videos on average over the fastest known implementations, while slightly improving the accuracy. Finally, we also studied the parallelization of the cascade training process and its scalability under SMP platforms. The proposed parallelization strategy exploits both task and data-level parallelism and achieves a 3.5X speedup over single-threaded implementations http://hdl.handle.net/2117/18360 Title: Task-based parallel breadth-first search in heterogeneous environments Authors: Munguía, Lluis Miquel; Bader, David A.; Ayguadé Parra, Eduard Abstract: Breadth-first search (BFS) is an essential graph traversal strategy widely used in many computing applications. Because of its irregular data access patterns, BFS has become a non-trivial problem hard to parallelize efficiently. In this paper, we introduce a parallelization strategy that allows the load balancing of computation resources as well as the execution of graph traversals in hybrid environments composed of CPUs and GPUs. To achieve that goal, we use a fine-grained task-based parallelization scheme and the OmpSs programming model. We obtain processing rates up to 2.8 billion traversed edges per second with a single GPU and a multi-core processor. Our study shows high processing rates are achievable with hybrid environments despite the GPU communication latency and memory coherence. Mon, 18 Mar 2013 10:13:40 GMT http://hdl.handle.net/2117/18360 2013-03-18T10:13:40Z Munguía, Lluis Miquel; Bader, David A.; Ayguadé Parra, Eduard no Breadth-first search (BFS) is an essential graph traversal strategy widely used in many computing applications. Because of its irregular data access patterns, BFS has become a non-trivial problem hard to parallelize efficiently. In this paper, we introduce a parallelization strategy that allows the load balancing of computation resources as well as the execution of graph traversals in hybrid environments composed of CPUs and GPUs. To achieve that goal, we use a fine-grained task-based parallelization scheme and the OmpSs programming model. We obtain processing rates up to 2.8 billion traversed edges per second with a single GPU and a multi-core processor. Our study shows high processing rates are achievable with hybrid environments despite the GPU communication latency and memory coherence.