http://hdl.handle.net/2117/3111 Tue, 18 Jun 2013 20:42:25 GMT 2013-06-18T20:42:25Z webmaster.bupc@upc.edu Universitat Politècnica de Catalunya. Servei de Biblioteques i Documentació no http://hdl.handle.net/2117/19516 Title: Evaluación formativa usando exámenes no presenciales Authors: López Álvarez, David; Sánchez Carracedo, Fermín; Cruz Díaz, Josep Llorenç; Fernández Jiménez, Agustín Abstract: Los exámenes tradicionales están orientados a la evaluación sumativa, no a la formativa, y provocan un aprendizaje superficial, más que un aprendizaje profundo. Su objetivo es evaluar, no facilitar el aprendizaje. Los estudiantes perciben que su futuro a corto plazo depende de su nota en un examen, por lo que orientan su estudio a aprobar dicho examen. En este artículo se exponen las ventajas e inconvenientes de realizar un examen no presencial, con evaluación sumativa y formativa, que los estudiantes realizan fuera de clase a lo largo de un periodo de tiempo mucho más largo que el de un examen tradicional, lo que les ayuda a conseguir un aprendizaje profundo. Traditional exams are focused on the summative assessment, not on the formative one. Its aim is to evaluate, not to facilitate learning, so it results in superficial learning rather than deep learning. Thus, students perceive that their short-term future depends on their note in the exam, so their study is guided to pass the examination. In this paper we propose a take-home exam in which students have more time to solve the questions and are not restricted by the sources they can consult, thereby providing a highly educational task in which students experience a deep learning process. Wed, 05 Jun 2013 09:50:29 GMT http://hdl.handle.net/2117/19516 2013-06-05T09:50:29Z López Álvarez, David; Sánchez Carracedo, Fermín; Cruz Díaz, Josep Llorenç; Fernández Jiménez, Agustín no Modelos de evaluación, Evaluación formativa, Evaluación sumativa, Evaluación de competencias, Modelos de aprendizaje Los exámenes tradicionales están orientados a la evaluación sumativa, no a la formativa, y provocan un aprendizaje superficial, más que un aprendizaje profundo. Su objetivo es evaluar, no facilitar el aprendizaje. Los estudiantes perciben que su futuro a corto plazo depende de su nota en un examen, por lo que orientan su estudio a aprobar dicho examen. En este artículo se exponen las ventajas e inconvenientes de realizar un examen no presencial, con evaluación sumativa y formativa, que los estudiantes realizan fuera de clase a lo largo de un periodo de tiempo mucho más largo que el de un examen tradicional, lo que les ayuda a conseguir un aprendizaje profundo. Traditional exams are focused on the summative assessment, not on the formative one. Its aim is to evaluate, not to facilitate learning, so it results in superficial learning rather than deep learning. Thus, students perceive that their short-term future depends on their note in the exam, so their study is guided to pass the examination. In this paper we propose a take-home exam in which students have more time to solve the questions and are not restricted by the sources they can consult, thereby providing a highly educational task in which students experience a deep learning process. http://hdl.handle.net/2117/19515 Title: Improving the resilience of an IDS against performance throttling attacks Authors: Sreekar Shenoy, Govind; Tubella Murgadas, Jordi; González Colás, Antonio María Abstract: Intrusion Detection Systems (IDS) have emerged as one of the most promising ways to secure systems in the network. To be effective against evasion attempts, the IDS must provide tight bounds on performance. Otherwise an adversary can bypass the IDS by carefully crafting and sending packets that throttle it. This can render the IDS ineffective, thus resulting in the network becoming vulnerable. We present a performance throttling attack mounted against the computationally intensive string matching algorithm. This algorithm performs string matching by traversing a finite-state-machine (FSM). We observe that there are some input bytes that sequentially traverse a chain of 30 pointers. This chain of traversal drastically degrades performance, and we observe a 22X performance drop in comparison to the average case performance. We investigate hardware and software mechanisms to counter this performance degradation. The software mechanism is targeted for commodity general purpose CPUs. While the hardware-based mechanism uses a parallel traversal suitable for network processor architectures. Our results show that our proposed mechanisms significantly improves (by over 3X magnitude) string matching algorithm’s worst performing cases. Wed, 05 Jun 2013 09:31:15 GMT http://hdl.handle.net/2117/19515 2013-06-05T09:31:15Z Sreekar Shenoy, Govind; Tubella Murgadas, Jordi; González Colás, Antonio María no Intrusion Detection Systems (IDS) have emerged as one of the most promising ways to secure systems in the network. To be effective against evasion attempts, the IDS must provide tight bounds on performance. Otherwise an adversary can bypass the IDS by carefully crafting and sending packets that throttle it. This can render the IDS ineffective, thus resulting in the network becoming vulnerable. We present a performance throttling attack mounted against the computationally intensive string matching algorithm. This algorithm performs string matching by traversing a finite-state-machine (FSM). We observe that there are some input bytes that sequentially traverse a chain of 30 pointers. This chain of traversal drastically degrades performance, and we observe a 22X performance drop in comparison to the average case performance. We investigate hardware and software mechanisms to counter this performance degradation. The software mechanism is targeted for commodity general purpose CPUs. While the hardware-based mechanism uses a parallel traversal suitable for network processor architectures. Our results show that our proposed mechanisms significantly improves (by over 3X magnitude) string matching algorithm’s worst performing cases. http://hdl.handle.net/2117/19454 Title: Exámenes no presenciales Authors: López Álvarez, David; Sánchez Carracedo, Fermín; Cruz Díaz, Josep Llorenç; Fernández Jiménez, Agustín Abstract: Los exámenes tradicionales están orientados a la evaluación sumativa, no a la formativa. Su objetivo es evaluar, no facilitar el aprendizaje, y debido a ello provocan un aprendizaje superficial más que un aprendizaje profundo: los estudiantes perciben que su futuro a corto plazo depende de su nota en un examen, por lo que orientan su estudio a aprobar dicho examen. En este artículo se propone una alternativa: un examen no presencial que realiza tanto evaluación sumativa como formativa. Es un tipo de examen que los estudiantes realizan fuera de clase a lo largo de un periodo de tiempo mucho más largo que el de un examen tradicional, lo que les ayuda a conseguir un aprendizaje profundo. En el artículo se presentan los resultados de una experiencia de 11 semestres utilizando este tipo de exámenes en una asignatura de la Facultat d’Informàtica de Barcelona. Thu, 30 May 2013 09:41:44 GMT http://hdl.handle.net/2117/19454 2013-05-30T09:41:44Z López Álvarez, David; Sánchez Carracedo, Fermín; Cruz Díaz, Josep Llorenç; Fernández Jiménez, Agustín no Modelos de evaluación, Evaluación formativa, Evaluación sumativa, Evaluación de competencias, Modelos de aprendizaje Los exámenes tradicionales están orientados a la evaluación sumativa, no a la formativa. Su objetivo es evaluar, no facilitar el aprendizaje, y debido a ello provocan un aprendizaje superficial más que un aprendizaje profundo: los estudiantes perciben que su futuro a corto plazo depende de su nota en un examen, por lo que orientan su estudio a aprobar dicho examen. En este artículo se propone una alternativa: un examen no presencial que realiza tanto evaluación sumativa como formativa. Es un tipo de examen que los estudiantes realizan fuera de clase a lo largo de un periodo de tiempo mucho más largo que el de un examen tradicional, lo que les ayuda a conseguir un aprendizaje profundo. En el artículo se presentan los resultados de una experiencia de 11 semestres utilizando este tipo de exámenes en una asignatura de la Facultat d’Informàtica de Barcelona. http://hdl.handle.net/2117/19428 Title: Improving the performance efficiency of an IDS by exploiting temporal locality in network traffic Authors: Sreekar Shenoy, Govind; Tubella Murgadas, Jordi; González Colás, Antonio María Abstract: Network traffic has traditionally exhibited temporal locality in the header field of packets. Such locality is intuitive and is a consequence of the semantics of network protocols. However, in contrast, the locality in the packet payload has not been studied in significant detail. In this work we study temporal locality in the packet payload. Temporal locality can also be viewed as redundancy, and we observe significant redundancy in the packet payload. We investigate mechanisms to exploit it in a networking application. We choose Intrusion Detection Systems (IDS) as a case study. An IDS like the popular Snort operates by scanning packet payload for known attack strings. It first builds a Finite State Machine (FSM) from a database of attack strings, and traverses this FSM using bytes from the packet payload. So temporal locality in network traffic provides us an opportunity to accelerate this FSM traversal. Our mechanism dynamically identifies redundant bytes in the packet and skips their redundant FSM traversal. We further parallelize our mechanism by performing the redundancy identification concurrently with stages of Snort packet processing. IDS are commonly deployed in commodity processors, and we evaluate our mechanism on an Intel Core i3. Our performance study indicates that the length of the redundant chunk is a key factor in performance. We also observe important performance benefits in deploying our redundancy-aware mechanism in the Snort IDS[32]. Tue, 28 May 2013 11:41:21 GMT http://hdl.handle.net/2117/19428 2013-05-28T11:41:21Z Sreekar Shenoy, Govind; Tubella Murgadas, Jordi; González Colás, Antonio María no Deep packet inspection, Intrusion detection systems, Software caches, System performance evaluation, Temporal locality Network traffic has traditionally exhibited temporal locality in the header field of packets. Such locality is intuitive and is a consequence of the semantics of network protocols. However, in contrast, the locality in the packet payload has not been studied in significant detail. In this work we study temporal locality in the packet payload. Temporal locality can also be viewed as redundancy, and we observe significant redundancy in the packet payload. We investigate mechanisms to exploit it in a networking application. We choose Intrusion Detection Systems (IDS) as a case study. An IDS like the popular Snort operates by scanning packet payload for known attack strings. It first builds a Finite State Machine (FSM) from a database of attack strings, and traverses this FSM using bytes from the packet payload. So temporal locality in network traffic provides us an opportunity to accelerate this FSM traversal. Our mechanism dynamically identifies redundant bytes in the packet and skips their redundant FSM traversal. We further parallelize our mechanism by performing the redundancy identification concurrently with stages of Snort packet processing. IDS are commonly deployed in commodity processors, and we evaluate our mechanism on an Intel Core i3. Our performance study indicates that the length of the redundant chunk is a key factor in performance. We also observe important performance benefits in deploying our redundancy-aware mechanism in the Snort IDS[32]. http://hdl.handle.net/2117/19426 Title: Hardware/software mechanisms for protecting an IDS against algorithmic complexity attacks Authors: Sreekar Shenoy, Govind; Tubella Murgadas, Jordi; González Colás, Antonio María Abstract: Intrusion Detection Systems (IDS) have emerged as one of the most promising ways to secure systems in the network. An IDS like the popular Snort[17] detects attacks on the network using a database of previous attacks. So in order to detect these attack strings in the packet, Snort uses the Aho-Corasick algorithm. This algorithm first constructs a Finite State Machine (FSM) from the attack strings, and subsequently traverses the FSM using bytes from the packet. We observe that there are input bytes that result in a traversal of a series of FSM states (also viewed as pointers). This chain of pointer traversal significantly degrades (22X) the processing time of an input byte. Such a wide variance in the processing time of an input byte can be exploited by an adversary to throttle the IDS. If the IDS is unable to keep pace with the network traffic, the IDS gets disabled. So in the process the network becomes vulnerable. Attacks done in this manner are referred to as algorithmic complexity attacks, and arise due to weaknesses in IDS processing. In this work, we explore defense mechanisms to the above outlined algorithmic complexity attack. Our proposed mechanisms provide over 3X improvement in the worst-case performance. Tue, 28 May 2013 10:21:42 GMT http://hdl.handle.net/2117/19426 2013-05-28T10:21:42Z Sreekar Shenoy, Govind; Tubella Murgadas, Jordi; González Colás, Antonio María no Defense mechanisms, Hardware support, Intrusion detection systems Intrusion Detection Systems (IDS) have emerged as one of the most promising ways to secure systems in the network. An IDS like the popular Snort[17] detects attacks on the network using a database of previous attacks. So in order to detect these attack strings in the packet, Snort uses the Aho-Corasick algorithm. This algorithm first constructs a Finite State Machine (FSM) from the attack strings, and subsequently traverses the FSM using bytes from the packet. We observe that there are input bytes that result in a traversal of a series of FSM states (also viewed as pointers). This chain of pointer traversal significantly degrades (22X) the processing time of an input byte. Such a wide variance in the processing time of an input byte can be exploited by an adversary to throttle the IDS. If the IDS is unable to keep pace with the network traffic, the IDS gets disabled. So in the process the network becomes vulnerable. Attacks done in this manner are referred to as algorithmic complexity attacks, and arise due to weaknesses in IDS processing. In this work, we explore defense mechanisms to the above outlined algorithmic complexity attack. Our proposed mechanisms provide over 3X improvement in the worst-case performance. http://hdl.handle.net/2117/19158 Title: DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support Authors: Pavlou, Demos; Gibert Codina, Enric; Latorre, Fernando; González Colás, Antonio María Abstract: Dynamic Binary Translators (DBT) and Dynamic Binary Opti- mization (DBO) by software are used widely for several reasons including performance, design simplification and virtualization. However, the software layer in such systems introduces non- negligible overheads which affect performance and user experi- ence. Hence, reducing DBT/DBO overheads is of paramount im- portance. In addition, reduced overheads have interesting collateral effects in the rest of the software layer, such as allowing optimiza- tions to be applied earlier. A cost-effective solution to this problem is to provide hardware support to speed up the primitives of the software layer, paying special attention to automate DBT/DBO mechanisms and leave the heuristics to the software, which is more flexible. In this work, we have characterized the overheads of a DBO sys- tem using DynamoRIO implementing several basic optimizations. We have seen that the computation of the Data Dependence Graph (DDG) accounts for 5%-10% of the execution time. For this rea- son, we propose to add hardware support for this task in the form of a new functional unit, called DDGacc, which is integrated in a conventional pipeline processor and is operated through new ISA instructions. Our evaluation shows that DDGacc reduces the cost of computing the DDG by 32x, which reduces overall execution time by 5%-10% on average and up to 18% for applications where the DBO optimizes large code footprints. Fri, 10 May 2013 12:30:37 GMT http://hdl.handle.net/2117/19158 2013-05-10T12:30:37Z Pavlou, Demos; Gibert Codina, Enric; Latorre, Fernando; González Colás, Antonio María no co-designed processors, dynamic binary optimization, hardware acceleration, start-up overhead Dynamic Binary Translators (DBT) and Dynamic Binary Opti- mization (DBO) by software are used widely for several reasons including performance, design simplification and virtualization. However, the software layer in such systems introduces non- negligible overheads which affect performance and user experi- ence. Hence, reducing DBT/DBO overheads is of paramount im- portance. In addition, reduced overheads have interesting collateral effects in the rest of the software layer, such as allowing optimiza- tions to be applied earlier. A cost-effective solution to this problem is to provide hardware support to speed up the primitives of the software layer, paying special attention to automate DBT/DBO mechanisms and leave the heuristics to the software, which is more flexible. In this work, we have characterized the overheads of a DBO sys- tem using DynamoRIO implementing several basic optimizations. We have seen that the computation of the Data Dependence Graph (DDG) accounts for 5%-10% of the execution time. For this rea- son, we propose to add hardware support for this task in the form of a new functional unit, called DDGacc, which is integrated in a conventional pipeline processor and is operated through new ISA instructions. Our evaluation shows that DDGacc reduces the cost of computing the DDG by 32x, which reduces overall execution time by 5%-10% on average and up to 18% for applications where the DBO optimizes large code footprints. http://hdl.handle.net/2117/18906 Title: The contribution of Type IA supernovae to the galactic iron abundances Authors: Bravo Guil, Eduardo; Isern Vilaboy, Jordi; Canal Corretger, Ramon Abstract: The thermonuclear explosion of a mass-accreting white dwarf in a close binary system is thought to be at the origin of Type Ia supernovae. Standard models, which ignite carbon at densities higher than 2-4 x 10 exp 9 g/cu cm, give, however, a large production of species like Fe-54, Ni-58, and Cr-54, which has been regarded as incompatible with the solar system abundances. In this paper we analyze the weight of the constraints imposed by nucleosynthesis of the Fe-peak nuclides to the aforementioned scenario for Type Ia supernovae when the contribution of Type II and Type Ib supernovae to the galactic iron abundances is also taken into account. We find that the production of the aforementioned nuclides predicted by standard SNIa models is in fact compatible with the solar system abundances when the yields from gravitational-collapse supernovae are adjusted to reproduce the Ni abundances in low-metallicity stars. Fri, 19 Apr 2013 17:11:40 GMT http://hdl.handle.net/2117/18906 2013-04-19T17:11:40Z Bravo Guil, Eduardo; Isern Vilaboy, Jordi; Canal Corretger, Ramon no The thermonuclear explosion of a mass-accreting white dwarf in a close binary system is thought to be at the origin of Type Ia supernovae. Standard models, which ignite carbon at densities higher than 2-4 x 10 exp 9 g/cu cm, give, however, a large production of species like Fe-54, Ni-58, and Cr-54, which has been regarded as incompatible with the solar system abundances. In this paper we analyze the weight of the constraints imposed by nucleosynthesis of the Fe-peak nuclides to the aforementioned scenario for Type Ia supernovae when the contribution of Type II and Type Ib supernovae to the galactic iron abundances is also taken into account. We find that the production of the aforementioned nuclides predicted by standard SNIa models is in fact compatible with the solar system abundances when the yields from gravitational-collapse supernovae are adjusted to reproduce the Ni abundances in low-metallicity stars. http://hdl.handle.net/2117/18905 Title: On the photometric homogeneity of type IA supernovae Authors: Bravo Guil, Eduardo; Domínguez, Inmaculada; Isern, Jordi; Canal Corretger, Ramon; Höflich, P.; Labay, Javier Abstract: The dependence of the characteristics of the light curves of Type Ia supernovae on the ignition density of the progenitor white dwarf is studied with the aid of two models of propagation of the thermonuclear burning front: as a deflagration and as a delayed detonation. The light curve is computed from opacities which take into account the velocity gradients. The results show that in all cases the resulting light curves roughly agree with observations and that they are not sensitive to the ignition density of the white dwarf. Only the model corresponding to a deflagration starting at a density of 8 x 10 exp 9 g/cu cm shows a deviation from the general behavior, having a significantly lower luminosity at maximum. A dispersion of about 1000 km/s is found in the computed expansion velocities at maximum, which compares well with that found in the observations. Fri, 19 Apr 2013 17:02:57 GMT http://hdl.handle.net/2117/18905 2013-04-19T17:02:57Z Bravo Guil, Eduardo; Domínguez, Inmaculada; Isern, Jordi; Canal Corretger, Ramon; Höflich, P.; Labay, Javier no The dependence of the characteristics of the light curves of Type Ia supernovae on the ignition density of the progenitor white dwarf is studied with the aid of two models of propagation of the thermonuclear burning front: as a deflagration and as a delayed detonation. The light curve is computed from opacities which take into account the velocity gradients. The results show that in all cases the resulting light curves roughly agree with observations and that they are not sensitive to the ignition density of the white dwarf. Only the model corresponding to a deflagration starting at a density of 8 x 10 exp 9 g/cu cm shows a deviation from the general behavior, having a significantly lower luminosity at maximum. A dispersion of about 1000 km/s is found in the computed expansion velocities at maximum, which compares well with that found in the observations. http://hdl.handle.net/2117/18455 Title: A Novel variation-tolerant 4T-DRAM with enhance soft-error tolerance Authors: Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Enrico; González Colás, Antonio María; Rubio Sola, Jose Antonio Abstract: In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. The retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment. Thu, 21 Mar 2013 13:41:03 GMT http://hdl.handle.net/2117/18455 2013-03-21T13:41:03Z Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Enrico; González Colás, Antonio María; Rubio Sola, Jose Antonio no In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. The retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment. http://hdl.handle.net/2117/18448 Title: Analysis of CPI variance for dynamic binary translators/optimizers modules Authors: Brankovic, Aleksandar; Stavrou, Kyriakos; Gibert Codina, Enric; González Colás, Antonio María Abstract: Dynamic Binary Translators and Optimizers (DBTOs) have been established as a hot research topic. They are used in many different systems, such as emulation, instrumentation tools and innovative HW/SW co-designed microarchitectures. Although many researchers worked on characterizing and reducing the emulation overhead, to the best of our knowledge, there are no published results that explain how the microarchitectural behavior of the emulation software is affected by the guest application which is emulated. In this paper we study the DBTO as an independent application, which is divided into the modules with specific functionality. We show the variance in microarchitectural behavior of DBTO among 48 applications. Moreover, we locate and explain the sources of variance. The results show that the variance is caused by interaction with the code cache (emulated application) and non uniform module execution characteristics. The insights presented in this paper can be exploited towards the design of more efficient DBTOs Wed, 20 Mar 2013 19:11:15 GMT http://hdl.handle.net/2117/18448 2013-03-20T19:11:15Z Brankovic, Aleksandar; Stavrou, Kyriakos; Gibert Codina, Enric; González Colás, Antonio María no Dynamic Binary Translators and Optimizers (DBTOs) have been established as a hot research topic. They are used in many different systems, such as emulation, instrumentation tools and innovative HW/SW co-designed microarchitectures. Although many researchers worked on characterizing and reducing the emulation overhead, to the best of our knowledge, there are no published results that explain how the microarchitectural behavior of the emulation software is affected by the guest application which is emulated. In this paper we study the DBTO as an independent application, which is divided into the modules with specific functionality. We show the variance in microarchitectural behavior of DBTO among 48 applications. Moreover, we locate and explain the sources of variance. The results show that the variance is caused by interaction with the code cache (emulated application) and non uniform module execution characteristics. The insights presented in this paper can be exploited towards the design of more efficient DBTOs http://hdl.handle.net/2117/18242 Title: Setting an error detection infrastructure with low cost acoustics wave detectors Authors: Upasani, Gaurang; Vera Rivera, Francisco Javier; González Colás, Antonio María Abstract: The continuing decrease in dimensions and operating voltage of transistors has increased their sensitivity against radiation phenomena making soft errors an important challenge in future chip multiprocessors (CMPs). Hence, new techniques for detecting errors in the logic and memories that allow meeting the desired failures-in-time (FIT) budget in CMPs are required. This paper proposes a low-cost dynamic particle strike detection mechanism through acoustic wave detectors. Our results show that our mechanism can protect both the logic and the memory arrays. As a case study, we also show how this technique can be combined with error codes to protect the last-level cache at low cost. Tue, 12 Mar 2013 18:17:30 GMT http://hdl.handle.net/2117/18242 2013-03-12T18:17:30Z Upasani, Gaurang; Vera Rivera, Francisco Javier; González Colás, Antonio María no The continuing decrease in dimensions and operating voltage of transistors has increased their sensitivity against radiation phenomena making soft errors an important challenge in future chip multiprocessors (CMPs). Hence, new techniques for detecting errors in the logic and memories that allow meeting the desired failures-in-time (FIT) budget in CMPs are required. This paper proposes a low-cost dynamic particle strike detection mechanism through acoustic wave detectors. Our results show that our mechanism can protect both the logic and the memory arrays. As a case study, we also show how this technique can be combined with error codes to protect the last-level cache at low cost. http://hdl.handle.net/2117/18207 Title: Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs Authors: Jaksic, Zoran; Canal Corretger, Ramon Abstract: In this paper, we pr esent the dynamic 3T memory cell for future 10nm tri-gate FinFETs as a potential replacement for classical 6T SRAM cell for implementation in high speed cache memories. We investigate read access time, retention time, and static power consumption of the cell when it is exposed to the effects of process and environmental variations. Process variations are extracted from the ITRS predictions and they are modeled at device level. For simulation, we use 10nm SOI tri-gate FinFET BSIM-CMG model card developed by the University of Glasgow, Device Modeling Group. When compared to the classical 6T SRAM, 3T cell has 40% smaller area, leakage is reduced up to 14 times while access time is approximately the same. In order to achieve higher retention times, we propose several cell extensions which, at the same time, enable post- fabrication/run-time adaptability. Tue, 12 Mar 2013 13:17:05 GMT http://hdl.handle.net/2117/18207 2013-03-12T13:17:05Z Jaksic, Zoran; Canal Corretger, Ramon no In this paper, we pr esent the dynamic 3T memory cell for future 10nm tri-gate FinFETs as a potential replacement for classical 6T SRAM cell for implementation in high speed cache memories. We investigate read access time, retention time, and static power consumption of the cell when it is exposed to the effects of process and environmental variations. Process variations are extracted from the ITRS predictions and they are modeled at device level. For simulation, we use 10nm SOI tri-gate FinFET BSIM-CMG model card developed by the University of Glasgow, Device Modeling Group. When compared to the classical 6T SRAM, 3T cell has 40% smaller area, leakage is reduced up to 14 times while access time is approximately the same. In order to achieve higher retention times, we propose several cell extensions which, at the same time, enable post- fabrication/run-time adaptability. http://hdl.handle.net/2117/18176 Title: A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance Authors: Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Enrico; González Colás, Antonio María; Rubio Sola, Jose Antonio Abstract: In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. The retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment Mon, 11 Mar 2013 14:33:59 GMT http://hdl.handle.net/2117/18176 2013-03-11T14:33:59Z Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Enrico; González Colás, Antonio María; Rubio Sola, Jose Antonio no In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. The retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment http://hdl.handle.net/2117/18025 Title: Reducing energy consumption in human-centric wireless sensor networks Authors: Meseguer Pallarès, Roc; Molina Clemente, Carlos; Ochoa, Sergio; Santos, Rodrigo Abstract: Energy consumption is a main research issue in wireless sensor networks; and particularly in those where nodes collaborate to reach a goal. This article explores the energy consumption in mobile devices participating in a human-based wireless sensor network. Specifically, the paper proposes the use of a message predictor to help detect and reduce the number of unnecessary control packets delivered by the nodes as a way to keep updated the network topology. In order to evaluate this proposal, the Optimized Link State Routing protocol was modified to add a message predictor between the routing and the network layers. Eleven simulations were performed using a particular setting. The preliminary results indicate the use of the message predictor can help reduce considerably the nodes energy consumption without affecting the routing capability of the protocol. Although these results are still preliminary, they are highly encouraging. Thu, 28 Feb 2013 17:25:11 GMT http://hdl.handle.net/2117/18025 2013-02-28T17:25:11Z Meseguer Pallarès, Roc; Molina Clemente, Carlos; Ochoa, Sergio; Santos, Rodrigo no Human-centric, wireless sensor network, energy consumption, messages prediction, opportunistic network Energy consumption is a main research issue in wireless sensor networks; and particularly in those where nodes collaborate to reach a goal. This article explores the energy consumption in mobile devices participating in a human-based wireless sensor network. Specifically, the paper proposes the use of a message predictor to help detect and reduce the number of unnecessary control packets delivered by the nodes as a way to keep updated the network topology. In order to evaluate this proposal, the Optimized Link State Routing protocol was modified to add a message predictor between the routing and the network layers. Eleven simulations were performed using a particular setting. The preliminary results indicate the use of the message predictor can help reduce considerably the nodes energy consumption without affecting the routing capability of the protocol. Although these results are still preliminary, they are highly encouraging. http://hdl.handle.net/2117/16935 Title: Cómo formar ingenieros en informática en la competencia sostenibilidad y compromiso social Authors: Franquesa, David; Cruz Díaz, Josep Llorenç; Álvarez Martínez, Carlos; Sánchez Carracedo, Fermín; Fernández Jiménez, Agustín; López Álvarez, David Abstract: In addition to he technical skills, the new trends in engineering education include the so-called professional skills. These skills are usually hard to teach and to evaluate, and some of them are difficult to include in technical subjects. In this paper, we analyze the "Sustainability and Social Responsibility" skill, an we present several techniques to develop it, both at the comprehension and the application levels according to the Bloom taxonomy. Besides, we also analyze the main requirements in an Educational Institution in order to implement this skill. / En los nuevos planes de estudios hay que desarrollar competencias que resultan novedosas: prácticamente no han sido trabajadas con anterioridad. Cómo enseñarlas y cómo evaluarlas es una preocupación para los diseñadores de los nuevos planes. Este artículo analiza la competencia "Sostenibilidad y Compromiso Social", explicando técnicas para desarrollarla tanto a nivel de comprensión como al de aplicación, según la taxonomía de Bloom, y analiza las condiciones que deben darse en un centro para poder implementar estas técnicas en las asignaturas de su plan de estudios. Fri, 16 Nov 2012 11:04:58 GMT http://hdl.handle.net/2117/16935 2012-11-16T11:04:58Z Franquesa, David; Cruz Díaz, Josep Llorenç; Álvarez Martínez, Carlos; Sánchez Carracedo, Fermín; Fernández Jiménez, Agustín; López Álvarez, David no Sostenibilidad, Organización de planes de estudio, Organización de la Universidad, Responsabilidad social, Professional skills, Social responsibility, Studies organization, Sustainability, University organization, Competencias transversales In addition to he technical skills, the new trends in engineering education include the so-called professional skills. These skills are usually hard to teach and to evaluate, and some of them are difficult to include in technical subjects. In this paper, we analyze the "Sustainability and Social Responsibility" skill, an we present several techniques to develop it, both at the comprehension and the application levels according to the Bloom taxonomy. Besides, we also analyze the main requirements in an Educational Institution in order to implement this skill. / En los nuevos planes de estudios hay que desarrollar competencias que resultan novedosas: prácticamente no han sido trabajadas con anterioridad. Cómo enseñarlas y cómo evaluarlas es una preocupación para los diseñadores de los nuevos planes. Este artículo analiza la competencia "Sostenibilidad y Compromiso Social", explicando técnicas para desarrollarla tanto a nivel de comprensión como al de aplicación, según la taxonomía de Bloom, y analiza las condiciones que deben darse en un centro para poder implementar estas técnicas en las asignaturas de su plan de estudios.