http://hdl.handle.net/2117/2138 Wed, 19 Jun 2013 23:34:26 GMT 2013-06-19T23:34:26Z webmaster.bupc@upc.edu Universitat Politècnica de Catalunya. Servei de Biblioteques i Documentació no http://hdl.handle.net/2117/19544 Title: Quasi-digital conversion for resistive devices: application in GMR-based IC current sensors Authors: Reig, C.; Cubells, Miquel; De Marcellis, A.; Madrenas Boadas, Jordi; Cardoso, S.; Freitas, P.P. Abstract: Resistive devices, including sensors, are used in a huge range of applications within different scenarios. When a complete system is considered, a quasi-digital output is often recommendable. If the conversion is operated at device level, some problems such as noise disturbs, insertion losses and so on, can be reduced. In this work, we describe a resistance-tofrequency (R-f) converter with a suggested application in low current monitoring by means of GiantMagnetoResistance (GMR) sensors. Specific devices have been designed and microfabricated. The system has been tested by means of discrete components with a PCB. The complete microsystem monolithic integration in a standard CMOS technology has been also analyzed. Wed, 12 Jun 2013 17:03:54 GMT http://hdl.handle.net/2117/19544 2013-06-12T17:03:54Z Reig, C.; Cubells, Miquel; De Marcellis, A.; Madrenas Boadas, Jordi; Cardoso, S.; Freitas, P.P. no Sensors, CMOS integrated circuits, Electric current measurement, Electron devices, Oscillators (electronic), Polychlorinated biphenyls Resistive devices, including sensors, are used in a huge range of applications within different scenarios. When a complete system is considered, a quasi-digital output is often recommendable. If the conversion is operated at device level, some problems such as noise disturbs, insertion losses and so on, can be reduced. In this work, we describe a resistance-tofrequency (R-f) converter with a suggested application in low current monitoring by means of GiantMagnetoResistance (GMR) sensors. Specific devices have been designed and microfabricated. The system has been tested by means of discrete components with a PCB. The complete microsystem monolithic integration in a standard CMOS technology has been also analyzed. http://hdl.handle.net/2117/19395 Title: A communication infrastructure for emulating large-scale neural networks models Authors: Barrera, A.G.; Moreno Aróstegui, Juan Manuel Abstract: This paper presents the SEPELYNS architecture that permits to in- terconnect multiple spiking neurons focused on hardware implementations. SEPELYNS can connect millions of neur ons with thousands of synapses per neuron in a layered fabric that provides some capabilities such as connectivity, expansion, flexibility, bio-plausibility and reusing of resources that allows si- mulation of very large networks. We presen t the three layers of this architecture (neuronal, network adapters and networks on chip layers) and explain its per- formance parameters such as throughput, latency and hardware resources. Some application examples of large neural networks on SEPELYNS are studied; these will show that use of on-chip parallel networks could permit the hardware simulation of populations of spiking neurons. Mon, 27 May 2013 08:33:20 GMT http://hdl.handle.net/2117/19395 2013-05-27T08:33:20Z Barrera, A.G.; Moreno Aróstegui, Juan Manuel no This paper presents the SEPELYNS architecture that permits to in- terconnect multiple spiking neurons focused on hardware implementations. SEPELYNS can connect millions of neur ons with thousands of synapses per neuron in a layered fabric that provides some capabilities such as connectivity, expansion, flexibility, bio-plausibility and reusing of resources that allows si- mulation of very large networks. We presen t the three layers of this architecture (neuronal, network adapters and networks on chip layers) and explain its per- formance parameters such as throughput, latency and hardware resources. Some application examples of large neural networks on SEPELYNS are studied; these will show that use of on-chip parallel networks could permit the hardware simulation of populations of spiking neurons. http://hdl.handle.net/2117/17846 Title: Sense/Drive Architecture for CMOS-MEMS Accelerometers with Relaxation Oscillator and TDC Authors: Michalik, Piotr Jozef; Madrenas Boadas, Jordi; Fernández Martínez, Daniel Mon, 18 Feb 2013 15:02:12 GMT http://hdl.handle.net/2117/17846 2013-02-18T15:02:12Z Michalik, Piotr Jozef; Madrenas Boadas, Jordi; Fernández Martínez, Daniel no http://hdl.handle.net/2117/16976 Title: The Equilibrium-action cycle as a mechanism for design-evolution integration in autonomous behavior design Authors: Olivier, Paul; Moreno Aróstegui, Juan Manuel Tue, 20 Nov 2012 13:05:58 GMT http://hdl.handle.net/2117/16976 2012-11-20T13:05:58Z Olivier, Paul; Moreno Aróstegui, Juan Manuel no http://hdl.handle.net/2117/16645 Title: LCMOS: Light-powered standard CMOS circuits Authors: Madrenas Boadas, Jordi; Fernández Martínez, Daniel; Wang, Chunyan Abstract: LCMOS, a harvest-use light-powered scheme for standard CMOS circuits based on photogenerated currents in the drain-substrate PN junction of both PMOS and NMOS transistors is introduced. PMOS and NMOS bulks are groundconnected so the generated currents induce symmetrical positive and negative voltage at the PMOS and NMOS sources, respectively. Applying this approach to a CMOS inverter ring oscillator in 150 nm technology, simulations show that nearly 1 Vpp signal range can be obtained. The operation of a simple 4- bit counter is also illustrated. The light-powering technique can be applied almost directly to digital standard cells in ultra-lowpower applications with modest processing speed requirements. Thu, 04 Oct 2012 12:00:10 GMT http://hdl.handle.net/2117/16645 2012-10-04T12:00:10Z Madrenas Boadas, Jordi; Fernández Martínez, Daniel; Wang, Chunyan no LCMOS, a harvest-use light-powered scheme for standard CMOS circuits based on photogenerated currents in the drain-substrate PN junction of both PMOS and NMOS transistors is introduced. PMOS and NMOS bulks are groundconnected so the generated currents induce symmetrical positive and negative voltage at the PMOS and NMOS sources, respectively. Applying this approach to a CMOS inverter ring oscillator in 150 nm technology, simulations show that nearly 1 Vpp signal range can be obtained. The operation of a simple 4- bit counter is also illustrated. The light-powering technique can be applied almost directly to digital standard cells in ultra-lowpower applications with modest processing speed requirements. http://hdl.handle.net/2117/14496 Title: Continuous-time CMOS adaptive asynchronous sigma-delta modulator approximating low-fs low-inband-error on-chip wideband power amplifier Authors: Alarcón Cot, Eduardo José; Fernández, Diego; García Tormo, Albert; Madrenas Boadas, Jordi; Poveda López, Alberto Abstract: A mixed-signal continuous-time-processing standard CMOS implementation of an asynchronous sigma-delta modulator aimed to drive a switching amplifier operating as an on-chip wideband adaptive power supply is presented in this work. The paper first briefly discusses the fundamental limit tracking capabilities of a two-level switching signal to inband-error-free track a bandlimited signal with minimum average switching frequency. It is argued the adequacy of an adaptive asynchronous sigma-delta modulator (AAΣΔ) to approximate such fundamental characteristics. The second part of the paper presents mixed-signal design details of the various subcircuits implementing a CMOS low-power digitally-programmable AAΣΔ modulator, with 7 MHz average switching frequency operation and 1000 µm × 640 µm area occupancy. Thu, 12 Jan 2012 19:13:58 GMT http://hdl.handle.net/2117/14496 2012-01-12T19:13:58Z Alarcón Cot, Eduardo José; Fernández, Diego; García Tormo, Albert; Madrenas Boadas, Jordi; Poveda López, Alberto no A mixed-signal continuous-time-processing standard CMOS implementation of an asynchronous sigma-delta modulator aimed to drive a switching amplifier operating as an on-chip wideband adaptive power supply is presented in this work. The paper first briefly discusses the fundamental limit tracking capabilities of a two-level switching signal to inband-error-free track a bandlimited signal with minimum average switching frequency. It is argued the adequacy of an adaptive asynchronous sigma-delta modulator (AAΣΔ) to approximate such fundamental characteristics. The second part of the paper presents mixed-signal design details of the various subcircuits implementing a CMOS low-power digitally-programmable AAΣΔ modulator, with 7 MHz average switching frequency operation and 1000 µm × 640 µm area occupancy. http://hdl.handle.net/2117/14246 Title: Best-basis development towards the automatical detection of otolith irregularities in fishes Authors: Soria Pérez, José Antonio; Parisi Baradad, Vicenç Abstract: The application of feature extraction methodologies and the detection of patterns in sagitae otoliths, which are calcified structures in the inner ear of teleostean fishes, has lead to great knowledge of marine biology during the last decades in order to manage and control its sustainability. A main limitation of the use of statistical analysis and Fourier methods rely on their incapacity to locate irregularities and explain them from a more structural, or even physical, point of view. This matter has been addressed recently by means of the Best-Basis paradigm which combines robust description methods, such as the Wavelet Transform, and the potential of statistical analysis in order to fully automate the selection process of efficient features. This paper is an attempt to readdress this paradigm towards this goal and contrasts other standard tools used in the field of otolith-based fish recognition. The proposed strategy involves the estimation of class distributions, discriminant measures and the search in the feature space. Wed, 14 Dec 2011 12:59:50 GMT http://hdl.handle.net/2117/14246 2011-12-14T12:59:50Z Soria Pérez, José Antonio; Parisi Baradad, Vicenç no The application of feature extraction methodologies and the detection of patterns in sagitae otoliths, which are calcified structures in the inner ear of teleostean fishes, has lead to great knowledge of marine biology during the last decades in order to manage and control its sustainability. A main limitation of the use of statistical analysis and Fourier methods rely on their incapacity to locate irregularities and explain them from a more structural, or even physical, point of view. This matter has been addressed recently by means of the Best-Basis paradigm which combines robust description methods, such as the Wavelet Transform, and the potential of statistical analysis in order to fully automate the selection process of efficient features. This paper is an attempt to readdress this paradigm towards this goal and contrasts other standard tools used in the field of otolith-based fish recognition. The proposed strategy involves the estimation of class distributions, discriminant measures and the search in the feature space. http://hdl.handle.net/2117/13975 Title: Equilibrium-Driven Adaptive Behavior Design Authors: Olivier, Paul; Moreno Aróstegui, Juan Manuel Abstract: In autonomous robotics, scalability is a primary discriminator for evaluating a behavior design methodology. Such a proposed methodology must also allow efficient and effective conversion from desired to implemented behavior. From the concepts of equilibrium and homeostasis, it follows that behavior could be seen as driven rather than controlled. Homeostatic variables allow the development of need elements to completely implement drive and processing elements in a synthetic nervous system. Furthermore, an autonomous robot or system must act with a sense of meaning as opposed to being a human-command executor. Learning is fundamental in adding adaptability, and its efficient implementation will directly improve scalability. It is shown how using classical conditioning to learn obstacle avoidance can be implemented with need elements instead of an existing artificial neural network (ANN) solution. Fri, 18 Nov 2011 19:30:20 GMT http://hdl.handle.net/2117/13975 2011-11-18T19:30:20Z Olivier, Paul; Moreno Aróstegui, Juan Manuel no In autonomous robotics, scalability is a primary discriminator for evaluating a behavior design methodology. Such a proposed methodology must also allow efficient and effective conversion from desired to implemented behavior. From the concepts of equilibrium and homeostasis, it follows that behavior could be seen as driven rather than controlled. Homeostatic variables allow the development of need elements to completely implement drive and processing elements in a synthetic nervous system. Furthermore, an autonomous robot or system must act with a sense of meaning as opposed to being a human-command executor. Learning is fundamental in adding adaptability, and its efficient implementation will directly improve scalability. It is shown how using classical conditioning to learn obstacle avoidance can be implemented with need elements instead of an existing artificial neural network (ANN) solution. http://hdl.handle.net/2117/13973 Title: Description of a fault tolerance system implemented in a hardware architecture with self-adaptive capabilities Authors: Soto, Javier; Moreno Aróstegui, Juan Manuel; Cabestany Moncusí, Joan Abstract: This paper describes a Fault Tolerance System (FTS) implemented in a new self-adaptive hardware architecture. This architecture is based on an array of cells that implements in a distributed way self-adaptive capabilities. The cell includes a configurable multiprocessor, so it can have between one and four processors working in parallel, with a programmable configuration mode that allows selecting the size of program and data memories. The self-elimination and self-replication capabilities of cell(s) are performed when the FTS detects a failure in any of the processors that include it, so that this cell(s) will be self-discarded for future implementations. Other self-adaptive capabilities of the system are self-routing, self-placement and runtime self-configuration. Fri, 18 Nov 2011 19:18:28 GMT http://hdl.handle.net/2117/13973 2011-11-18T19:18:28Z Soto, Javier; Moreno Aróstegui, Juan Manuel; Cabestany Moncusí, Joan no This paper describes a Fault Tolerance System (FTS) implemented in a new self-adaptive hardware architecture. This architecture is based on an array of cells that implements in a distributed way self-adaptive capabilities. The cell includes a configurable multiprocessor, so it can have between one and four processors working in parallel, with a programmable configuration mode that allows selecting the size of program and data memories. The self-elimination and self-replication capabilities of cell(s) are performed when the FTS detects a failure in any of the processors that include it, so that this cell(s) will be self-discarded for future implementations. Other self-adaptive capabilities of the system are self-routing, self-placement and runtime self-configuration. http://hdl.handle.net/2117/12186 Title: Bioinspired sensory integration for environment-perception embedded systems Authors: Madrenas Boadas, Jordi; Fernández Martínez, Daniel; Cosp Vilella, Jordi; Moreno Aróstegui, Juan Manuel; Martínez Alvarado, Luis Arturo; Sánchez Rivera, Giovanny Abstract: In this work, the architecture of a system intended for bioinspired environment perception is described. Considering the technology trends and applications requirements, the properties of such a system are discussed. The system consists of four main blocks: a) A set of different integrated microsensors and microactuators with the associated signal conditioning circuits; b) A data encoding block that in its simplest form performs spike encoding of information; c) a bioinspired digital processing block that efficiently emulates a spiking neuron network; d) a monitoring and self-adaptation block that provides feedback to the sensors and actuators. In its final implementation, the full system would eventually be almost fully integrated in a CMOS integrated circuit. Wed, 30 Mar 2011 09:55:35 GMT http://hdl.handle.net/2117/12186 2011-03-30T09:55:35Z Madrenas Boadas, Jordi; Fernández Martínez, Daniel; Cosp Vilella, Jordi; Moreno Aróstegui, Juan Manuel; Martínez Alvarado, Luis Arturo; Sánchez Rivera, Giovanny no In this work, the architecture of a system intended for bioinspired environment perception is described. Considering the technology trends and applications requirements, the properties of such a system are discussed. The system consists of four main blocks: a) A set of different integrated microsensors and microactuators with the associated signal conditioning circuits; b) A data encoding block that in its simplest form performs spike encoding of information; c) a bioinspired digital processing block that efficiently emulates a spiking neuron network; d) a monitoring and self-adaptation block that provides feedback to the sensors and actuators. In its final implementation, the full system would eventually be almost fully integrated in a CMOS integrated circuit. http://hdl.handle.net/2117/10928 Title: Density Local Discriminant Bases for the analysis of otolith morphology in fish identification applications Authors: Soria Pérez, José Antonio; Parisi Baradad, Vicenç; Lombarte, A. Mon, 10 Jan 2011 10:15:38 GMT http://hdl.handle.net/2117/10928 2011-01-10T10:15:38Z Soria Pérez, José Antonio; Parisi Baradad, Vicenç; Lombarte, A. no http://hdl.handle.net/2117/9894 Title: SpiNDeK: An integrated design tool for the multiprocessor emulation of complex bioinspired spiking neural networks Authors: Hauptvogel, Michael; Madrenas Boadas, Jordi; Moreno Aróstegui, Juan Manuel Abstract: SpiNDeK (Spiking Neural Network Design Kit) is an integrated design tool intended to support the development of emulation of complex bioinspired neural networks. In this work, the most relevant aspects of the tool are reported, regarding the generation of connections as well as synapse and neuron parameters of spiking neural networks as well as the automated code generation and simulation, ready to be executed by an ad-hoc parallel architecture. The tool is fully functional and has demonstrated its usefulness. Thu, 21 Oct 2010 10:41:10 GMT http://hdl.handle.net/2117/9894 2010-10-21T10:41:10Z Hauptvogel, Michael; Madrenas Boadas, Jordi; Moreno Aróstegui, Juan Manuel no SpiNDeK (Spiking Neural Network Design Kit) is an integrated design tool intended to support the development of emulation of complex bioinspired neural networks. In this work, the most relevant aspects of the tool are reported, regarding the generation of connections as well as synapse and neuron parameters of spiking neural networks as well as the automated code generation and simulation, ready to be executed by an ad-hoc parallel architecture. The tool is fully functional and has demonstrated its usefulness. http://hdl.handle.net/2117/8866 Title: JubiTool: Unified design flow for the perplexus SIMD hardware accelerator Authors: Robert, M.; Volken, H.; Brousse, O.; Guillot, J.; Gil, T.; Grize, F.; Sassatelli, G.; Moreno Aróstegui, Juan Manuel; Madrenas Boadas, Jordi; Villa, A. Abstract: This paper presents a new unified design flow developed within the Perplexus project that aims to accelerate parallelizable data-intensive applications in the context of ubiquitous computing. This contribution relies on the JubiTool: a set of integrated tools (JubiSplitter, JubiCompiler, UbiAssembler), allowing respectively to extract, compile and assemble parallelizable parts of applications described in Jubi language. Jubi is a modified Java agent based language (JADE) dedicated to the Ubichip (the bio-inspired chip developed within the confines of the Perplexus project). By appending hardware directives to a software agent description, the inherent flexibility of software is combined with the runtime performance of a hardware execution. In the case of typical Perplexus applications such as the Spiking Neural Network Simulator, this contribution takes profit of the intrinsic property of the Ubichip in terms of parallelism resulting in an expected speedup of at least one order of magnitude. Finally, this hybrid (SW/HW) flow could be easily modified and adapted to support other kind of distributed platforms Wed, 15 Sep 2010 07:40:26 GMT http://hdl.handle.net/2117/8866 2010-09-15T07:40:26Z Robert, M.; Volken, H.; Brousse, O.; Guillot, J.; Gil, T.; Grize, F.; Sassatelli, G.; Moreno Aróstegui, Juan Manuel; Madrenas Boadas, Jordi; Villa, A. no This paper presents a new unified design flow developed within the Perplexus project that aims to accelerate parallelizable data-intensive applications in the context of ubiquitous computing. This contribution relies on the JubiTool: a set of integrated tools (JubiSplitter, JubiCompiler, UbiAssembler), allowing respectively to extract, compile and assemble parallelizable parts of applications described in Jubi language. Jubi is a modified Java agent based language (JADE) dedicated to the Ubichip (the bio-inspired chip developed within the confines of the Perplexus project). By appending hardware directives to a software agent description, the inherent flexibility of software is combined with the runtime performance of a hardware execution. In the case of typical Perplexus applications such as the Spiking Neural Network Simulator, this contribution takes profit of the intrinsic property of the Ubichip in terms of parallelism resulting in an expected speedup of at least one order of magnitude. Finally, this hybrid (SW/HW) flow could be easily modified and adapted to support other kind of distributed platforms http://hdl.handle.net/2117/6725 Title: Synchronous digital implementation of the AER communication scheme for emulating large-scale spiking neural networks models Authors: Moreno Aróstegui, Juan Manuel; Madrenas Boadas, Jordi; Kotynia, L. Abstract: In this paper we shall present a fully synchronous digital implementation of the Address Event Representation (AER) communication scheme that has been used in the PERPLEXUS chip in order to permit the emulation of large-scale biologically inspired spiking neural networks models. By introducing specific commands in the AER protocol it is possible to distribute the AER bus among a large number of chips where the functionality of the spiking neurons is being emulated. A careful design of the AER encoder module using compact Content Addressable Memories (CAMs) allows for a feasible realization of large-scale models. Fri, 19 Mar 2010 15:55:46 GMT http://hdl.handle.net/2117/6725 2010-03-19T15:55:46Z Moreno Aróstegui, Juan Manuel; Madrenas Boadas, Jordi; Kotynia, L. no In this paper we shall present a fully synchronous digital implementation of the Address Event Representation (AER) communication scheme that has been used in the PERPLEXUS chip in order to permit the emulation of large-scale biologically inspired spiking neural networks models. By introducing specific commands in the AER protocol it is possible to distribute the AER bus among a large number of chips where the functionality of the spiking neurons is being emulated. A careful design of the AER encoder module using compact Content Addressable Memories (CAMs) allows for a feasible realization of large-scale models. http://hdl.handle.net/2117/6641 Title: Translinear signal processing circuits in standard CMOS FPAA Authors: Martínez Alvarado, Luis Arturo; Madrenas Boadas, Jordi; Fernández Martínez, Daniel Abstract: In this paper, the implementation of signal processing circuits on a novel translinear Field-Programmable Analog Array (FPAA) testchip is reported. The FPAA testchip is based on a 0.35-micron, fully CMOS translinear element, which is the core block of a reconfigurable analog cell. The FPAA embeds a 5 5 cell array. As implementation examples, a four-quadrant multiplier with five decade dynamic range and a programmable fourth-order low-pass filter with up to 7 MHz bandwidth have been mapped on the translinear FPAA. 14 cells have been used for the four-quadrant multiplier while 18 cells were needed for the fourth-order low-pass filter. Fri, 12 Mar 2010 15:59:53 GMT http://hdl.handle.net/2117/6641 2010-03-12T15:59:53Z Martínez Alvarado, Luis Arturo; Madrenas Boadas, Jordi; Fernández Martínez, Daniel no In this paper, the implementation of signal processing circuits on a novel translinear Field-Programmable Analog Array (FPAA) testchip is reported. The FPAA testchip is based on a 0.35-micron, fully CMOS translinear element, which is the core block of a reconfigurable analog cell. The FPAA embeds a 5 5 cell array. As implementation examples, a four-quadrant multiplier with five decade dynamic range and a programmable fourth-order low-pass filter with up to 7 MHz bandwidth have been mapped on the translinear FPAA. 14 cells have been used for the four-quadrant multiplier while 18 cells were needed for the fourth-order low-pass filter.