http://hdl.handle.net/2117/601 2013-05-21T10:41:17Z http://hdl.handle.net/2117/15667 Title: Process variability in sub-16nm bulk CMOS technology Authors: Rubio Sola, Jose Antonio; Figueras Pàmies, Joan; Vatajelu, Elena Ioana; Canal Corretger, Ramon Abstract: The document is part of deliverable D3.6 of the TRAMS Project (EU FP7 248789), of public nature, and shows and justifies the levels of variability used in the research project for sub-18nm bulk CMOS technologies. 2012-03-26T18:45:53Z http://hdl.handle.net/2117/15019 Title: Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors Authors: Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio Abstract: In this paper, we propose a dynamically tunable fine-grain body biasing mechanism to reduce active & standby leakage power in caches under process variations. 2012-02-08T12:50:44Z http://hdl.handle.net/2117/15007 Title: On the effectiveness of hybrid mechanisms on reduction of parametric failures in caches Authors: Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio Abstract: In this paper, we provide an insight on the different proactive read/write assist methods (wordline boosting & adaptive body biasing) that help in preventing (and reducing) parametric failures when coupled with reactive techniques like ECC and redundancy which cope with already existent failures. While proactive and reactive have been previously viewed as complementary techniques, we show that it is not necessarily the case when considering the benefits of such hybrid schemes. 2012-02-08T11:07:29Z http://hdl.handle.net/2117/13911 Title: vPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cells Authors: Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio Abstract: In this paper, we present an on-die post-silicon binning methodology that takes into account the effect of static and dynamic variations and categorizes every processor based on power/performance.The proposed scheme is composed of a discretization hardware that exploits the delay/leakage dependence on variability sources characteristic for categorization 2011-11-15T14:28:57Z http://hdl.handle.net/2117/13385 Title: FOCSI: A new layout regularity metric Authors: Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María Abstract: Digital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce these ICs systematic subwavelength lithography failures. However, there is no metric to evaluate and compare the layout regularity of those regular designs. In this paper we propose a new layout regularity metric called Fixed Origin Corner Square Inspection (FOCSI). FOCSI allows the comparison and quantification of designs in terms of regularity and for any given degree of granularity. When FOCSI is oriented to the evaluation of regularity while applying Lithography Enhancement Techniques, it comprehends layout layers measurements considering the optical interaction length and combines them to obtain the complete layout regularity measure. Examples are provided for 32-bit adders in the 90 nm technology node for the Standard Cell approach and for Via-Configurable Transistor Array regular designs. We show how layouts can be sorted accurately even if their degree of regularity is similar. Description: Technical Report 2011-09-29T08:11:25Z http://hdl.handle.net/2117/13055 Title: THERMAL OBSERVATION OF A MODULATED INPUT FOR A 2.5GHZ CMOS POWER AMPLIFIER Part 3: PA+Sensor layout integration and PVT analysis Authors: Martín, Mikel; González Jiménez, José Luis Abstract: The objective is to detect the impact of PVT variations (Process, Voltage and Temperature variations) on the figures of merit of a device. 2011-07-26T17:38:37Z http://hdl.handle.net/2117/13054 Title: THERMAL OBSERVATION OF A MODULATED INPUT FOR A 2.5GHZ CMOS POWER AMPLIFIER Part 2: Temperature Sensor Authors: Martín, Mikel; González Jiménez, José Luis Abstract: The temperature sensor used is based on the usual two bipolar transistors temperature sensor with some modifications to allow for external calibration (or “re-centering”). 2011-07-26T17:36:51Z http://hdl.handle.net/2117/13053 Title: THERMAL OBSERVATION OF A MODULATED INPUT FOR A 2.5GHZ CMOS POWER AMPLIFIER Part 1: Feasibility study Authors: Martin, Mikel; González Jiménez, José Luis Abstract: In this Project, the verification of the possibility of extraction of information of a modulated signal through no-invasive thermal measurements is done. The main objective is that using a non-invasive thermal technique, information about the PA can be extracted so that the PA’s efficiency can be improved. 2011-07-26T17:33:53Z http://hdl.handle.net/2117/12139 Title: CATRENE-PANAMA project review November 2010 Authors: González Jiménez, José Luis; Dufis, Cédric Yvan Abstract: Informe de progrés del projecte Europeu CATRENE-PANAMA sobre les tasques desenvolupades per el grup de recerca HiPICS de la UPC 2011-03-29T12:50:52Z http://hdl.handle.net/2117/11978 Title: Inforrme de la segona anualitat del projecte CATRENE-PANAMA per al programa AVANZA I+D Authors: González Jiménez, José Luis; Dufis, Cédric Yvan Abstract: Informe de les tasques i activitats desenvolupades al projecte europeu CATRENE-PANAMA durant l'any 2010 per el grup de recerca de la UPC HiPICS 2011-03-21T09:20:31Z http://hdl.handle.net/2117/11976 Title: CATRENE-PANAMA project review June 2010 Authors: González Jiménez, José Luis; Dufis, Cédric Yvan Abstract: Informe de progrés del projecte Europeu CATRENE-PANAMA sobre les tasques desenvolupades per el grup de recerca HiPICS de la UPC 2011-03-21T09:13:03Z http://hdl.handle.net/2117/8112 Title: CATRENE-PANAMA WP1: integrated PA Milestone M1.3 technology, approach & system choice for home networking Authors: Dufis, Cédric Yvan; Mateo Peña, Diego; Bofill, Adrià; González Jiménez, José Luis 2010-07-09T12:01:48Z http://hdl.handle.net/2117/2347 Title: Set-up of Assura RCX-HF tools for the AMS S35 process. Configuration files and usage guide. Authors: Aragonès Cervera, Xavier 2008-11-07T08:27:20Z http://hdl.handle.net/2117/1232 Title: Energy macro-model for on chip interconnection buses Authors: Mendoza Vázquez, Raymundo; Pons Solé, Marc; Moll Echeto, Francisco de Borja; Figueras, Joan Abstract: This report presents a fast method of evaluating the power consumption of a bus. Given an on-chip bus driver-interconnection-receiver design of N parallel lines,the objective is to develop its energy consumption macro-model. With this model we are be able to evaluate the energy metrics for the bus under a certain traffic and information coding. 2007-10-05T08:09:54Z