http://hdl.handle.net/2117/599 2013-05-25T01:31:41Z http://hdl.handle.net/2117/19217 Title: Inductor shielding strategies to protect mmW LC-VCOs from high frequency substrate noise Authors: Molina García, Marc; Aragonès Cervera, Xavier; Mateo Peña, Diego; González Jiménez, José Luis Abstract: This paper analyzes the impact of high-frequency substrate noise on two 60 GHz LC-VCOs that implement different strategies for inductor shielding, namely floating and grounded shields. An analytical model, which has previously shown very good accuracy up to 7 GHz, is used to identify the circuit parameters that determine the level of the spurs created by the noise. These parameters are individually evaluated for the two VCOs, identifying their relative responsibility for the observed noise effects. The analysis concludes that a floating inductor shield provides extra immunity compared to a grounded inductor shield, and that this advantage is essentially due to the improvement in the tank quality factor. The predictions of the analytical model are validated by comparing them with circuit simulations and measurements of the noise impact on the two VCOs manufactured in a 65 nm CMOS technology, proving its usefulness at mm-wave frequencies. 2013-05-14T17:11:01Z http://hdl.handle.net/2117/18806 Title: Spatially and frequency-resolved monitoring of intradie capacitive coupling by heterodyne excitation infrared lock-in thermography Authors: León, J.; Perpiñà, Xavier; Altet Sanahujes, Josep; Vallvehi, Miquel; Jordà, Xavier Abstract: This paper combines the infrared lock-in thermography (IR-LIT) and heterodyne excitation techniques to detect high-frequency capacitive currents due to intradie electrical coupling between microelectronic devices or more complex systems. Modulating the excitation with the heterodyne approach, we drive devices or complex systems with high frequency electrical signals in such a way that they behave as low frequency heat sources, modulating their temperature field at a frequency detectable by an IR-LIT system. This approach is analytically studied and extended to a bi-dimensional scenario, showing that the thermal information at low frequency depends on the electrical characteristics of the sample at high frequency. 2013-04-15T16:09:58Z http://hdl.handle.net/2117/16283 Title: TRAMS Project: variability and reliability of SRAM memories in sub-22nm bulk-CMOS technologies Authors: Canal Corretger, Ramon; Rubio Sola, Jose Antonio; ASenov, Asen; Brown, Andrew; Miranda, Miguel; Zuber, Paul; González Colás, Antonio María; Vera, Xavier Abstract: The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13 nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells and circuits. 2012-07-17T17:48:46Z http://hdl.handle.net/2117/16281 Title: Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy Authors: Aymerich Capdevila, Nivard; Rubio Sola, Jose Antonio Abstract: One of the main objectives of the data computing and memory industry is to keep and ever accelerate the increase of component density reached in nowadays integrated circuits in future technologies based on ultimate CMOS and new emerging research devices. The worldwide-accepted predictions with these technologies indicate a remarkable reduction of the components quality, because of the manufacturing process complexity and the erratic behavior of devices, causing a drop in the system reliability if we maintain the same design rules than today. Together with the introduction of new devices, new architectural design paradigms have to be included. Fault tolerant techniques are considered necessary and relevant in this scenario. In this paper we present a fault-tolerant nanoscale architecture based on the implementation of logic systems with Averaging Cells Linear Threshold Gates (AC-LTGs). We compare the tolerance to manufacturing and environment deviation of our approach and the well known NAND multiplexing technique. We show that the AC-LTG is a valuable alternative in specific nanoscale conditions. 2012-07-17T17:35:56Z http://hdl.handle.net/2117/16279 Title: Adaptive fault-tolerant architecture for unreliable technologies with heterogeneous variability Authors: Aymerich Capdevila, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio Abstract: This paper introduces an efficient adaptive redundant architecture, which makes use of the averaging cell (AVG) principle in order to improve the reliability of nanoscale circuits and systems. We propose an adaptive structure that is able to cope with nonhomogeneous variability and time-varying effects like degradation and external aggressions, which are expected to be key limiting factors in future technologies. First, we consider static heterogeneity of the input variability levels and derive a methodology to determine the weight values that maximize the reliability of the averaging system. The implementation of these optimal weights in the AVG gives place to the unbalanced AVG structure (U-AVG). Second, we take into consideration that circuits are exposed to time-dependent aggression factors, which can induce significant changes on the levels of variability, and introduce the adaptive AVG structure (AD-AVG). It embeds a learning mechanism based on a variability monitor that allows for the on-line input weight adaptation such that the actual weight configuration properly reflects the aging status. To evaluate the potential implications of our proposal, we compare the conventional AVG architecture with the unbalanced (U-AVG) and the adaptive (AD-AVG) approaches in terms of reliability and redundancy overhead by means of Monte Carlo simulations. Our results indicate that when AVG and U-AVG are exposed to the same static heterogeneous variability, U-AVG requires 4$times$ less redundancy for the same reliability target. Subsequently, we include temporal variation of input drifts in the simulations to reproduce the effects of aging and external aggressions and compare the AVG structures. Our experiments suggest that AD-AVG always provides the maximum reliability and the highest tolerance against degradation. We also analyze the impact of nonideal variability monitor on the effectiveness of the AD-AVG b- havior. Finally, specific reconfigurable hardware based on resistive switching crossbar structures is proposed for the implementation of AD-AVG. 2012-07-17T17:25:53Z http://hdl.handle.net/2117/16133 Title: On the electrical properties of slotted metallic planes in CMOS processes for RF and millimeter-wave applications Authors: González Jiménez, José Luis; Martineau, Baudouin; Belot, Didier Abstract: This paper presents a study of the effects of slottedmetallicplanes in passive structures built using CMOSprocesses for RF and millimeter-wave (mmW) applications. The impact of holes on the reference plane resistance and in the capacitance of any surrounding structure to the plane are investigated through electromagnetic (EM) simulations. Two analytical expressions are derived that capture the holes impact on the plane resistivity and on the dielectric constant of the materials found between the plane and the surroundings. These expressions are used to propose a simplified EM simulation methodology for on-chip microstrip transmission lines. 2012-06-25T14:34:46Z http://hdl.handle.net/2117/15777 Title: Prediction of the impact of substrate coupled switching noise on frequency synthesizers Authors: Osorio Tamayo, Juan Felipe; Aragonès Cervera, Xavier Abstract: This paper proposes a methodology to accurately predict the phase noise effects in frequency synthesizers as a consequence of switching noise coupled through the substrate. The method proposed is based on a phase model of a frequency synthesizer where each circuit block is characterized by complex noise sensitivity functions. Considering the phase information of the different contributors allows to evaluate the noise without overestimation, as well as identifying the main noise contributors. This information can then be used by designers to decide where to put the effort to mitigate the noise effects. The methodology is applied to a typical N-Integer frequency synthesizer based on a LC-VCO. Measurements on this frequency synthesizer implemented in a 0.35 μm CMOS technology have provided information of the relative importance of the noise aggressors, the effect of the loop on the phase noise, as well as comparison to the predictions obtained with the proposed methodology. 2012-05-03T18:31:41Z http://hdl.handle.net/2117/14366 Title: A 16-kV HBM RF ESD Protection Codesign for a 1-mW CMOS Direct Conversion Receiver Operating in the 2.4-GHz ISM Band Authors: González Jiménez, José Luis; Solar, H.; Adin, Iñigo; Mateo Peña, Diego; Berenguer, Roc Abstract: A decreasing-sized π -model electrostatic discharge (ESD) protection structure is presented and applied to protect against ESD stresses at the RF input pad of an ultra-low power CMOS front-end operating in the 2.4-GHz industrial-scientific-medical band. The proposed ESD protection structure is composed of a pair of ESD devices located near the RF pad, another pair close to the core circuit, and a high-quality integrated inductor connecting these two pairs. This structure can sustain a human body-model ESD level higher than 16 kV and a machine-model ESD level higher than 1 kV without degrading the RF performance of the front-end. A combined on-wafer transmission line pulse and RF test methodology for RF circuits is also presented confirming previous results. The front-end implements a zero-IF receiver. It has been implemented in a standard 2P6M 0.18-μm CMOS process. It exhibits a voltage gain of 24 dB and a single-sideband noise figure of 8.4 dB, which make it suitable for most of the 2.4-GHz wireless short-range communication transceivers. The power consumption is only 1.06 mW from a 1.2-V voltage supply. 2011-12-29T18:02:59Z http://hdl.handle.net/2117/14228 Title: New redundant logic design concept for high noise and low voltage scenarios Authors: García Leyva, Lancelot; Andrade Miceli, Dennis Michael; Gómez Fernández, Sergio; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio Abstract: This paper presents a new redundant logia design concept named Turtle Logic(TL).It is a new probabilistic logic method based on port redundancy and complementary data, oriented toward emerging technologies beyond CMOS, where the thermal noise could be predominant and the reliability of the future circuits could be limited. The TL is a technology independent method, which aims to improve error tolerance when these errors are caused by noise within logic and functional units, sequential elements, and in general synchronous pipeline Finite State Machines. Turtle Logic operation is based on the consistency relation of redundant inputs. In the case of discrepancy, the out put of the system keeps the previous value, therefore avoiding the propagation of incorrect inputs. A two’s complement 8x8-bit pipelined Baugh–Wooley multiplier is implemented, on which several experiments reveal a perfect tolerance (0%errors) to single line discrepancies for both primary and internal nodes, with a cost of lost clock periods between 6% and 25%. The error ratio for the proposed Turtle Logic implementation with double discrepancies in both true and complementary lines are lower than 0.1% when the noise affects primary input nodes, and lower than 0.9% when the noise affects internal nodes. 2011-12-13T11:15:31Z http://hdl.handle.net/2117/13143 Title: Design of a 2.5-GHZ QVCO robust against high frequency substrate noise Authors: Molina Garcia, Marc Manel; Gómez Salinas, Dídac; Aragonès Cervera, Xavier; Mateo Peña, Diego; González Jiménez, José Luis Abstract: This work presents the design procedure followed to obtain a low-power voltage-controlled oscillator (VCO) robust against high-frequency substrate noise, using as a demonstrator a 2.5 GHz VCO with quadrature outputs (QVCO) based on a 5-GHz LC tank resonant VCO (LC-VCO) and frequency divider. A simple, intuitive, and easy to handle analytical model is proposed to identify the design parameters that contribute to the performance degradation of LC-VCOs due to the effect of high frequency substrate noise. The guidelines obtained have been applied in the design of the low-power QVCO. Finally, the work discusses several trade-offs that can be used to maximize the immunity of a LC-VCO against substrate noise. 2011-08-31T11:01:24Z http://hdl.handle.net/2117/13127 Title: Survey of robustness enhancement techniques for wireless systems-on-a-chip and study of temperature as observable for process variations Authors: Onabajo, M.; Gómez Salinas, Dídac; Aldrete Vidrio, Eduardo; Altet Sanahujes, Josep; Mateo Peña, Diego; Silva-Martínez, José Abstract: Built-in test and on-chip calibration features are becoming essential for reliable wireless connectivity of next generation devices suffering from increasing process variations in CMOS technologies. This paper contains an overview of contemporary self-test and performance enhancement strategies for single-chip transceivers. In general, a trend has emerged to combine several techniques involving process variability monitoring, digital calibration, and tuning of analog circuits. Special attention is directed towards the investigation of temperature as an observable for process variations, given that thermal coupling through the silicon substrate has recently been demonstrated as mechanism to monitor the performances of analog circuits. Both Monte Carlo simulations and experimental results are presented in this paper to show that circuit-level specifications exhibit correlations with silicon surface temperature changes. Since temperature changes can be measured with efficient on-chip differential temperature sensors, a conceptual outline is given for the use of temperature sensors as alternative process variation monitors. 2011-08-26T08:28:27Z http://hdl.handle.net/2117/11201 Title: Lithography aware regular cell design based on a predictive technology model Authors: Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja Abstract: As semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated that layout regularity reduces the increasing impact of process variations on circuit performance and reliability. The aim of this paper is to present the layout design of a regular cell based on 1-D elements which reduces lithography perturbations (ALARC). We depict several undesirable lithography effects and how these distortions determine several layout parameters in order to achieve the required line-pattern resolution. Furthermore, it is shown how the measurement of leakage power consumption based on ideal layout is not a precise metric to evaluate circuit performance, especially for low power designs. Finally, the impact of lithography patterns on delay and leakage consumption of a typical cell is provided. 2011-01-25T14:07:25Z http://hdl.handle.net/2117/11053 Title: Process and temperature compensation for RF low-noise amplifiers and mixers Authors: Gómez Salinas, Dídac; Sroka, Milosz; González Jiménez, José Luis Abstract: Temperature and process variations have become key issues in the design of integrated circuits using deep submicron technologies. In RF front-end circuitry, many characteristics must be compensated in order to maintain acceptable performance across all process corners and throughout the temperature range. This paper proposes a new technique consisting of a compensation circuit that adapts and generates the appropriate bias voltage for LNAs and mixers so that the variability with temperature and process corners of their main performance metrics (S-parameters, gain, noise figure, etc.) is minimized. 2011-01-17T10:05:46Z http://hdl.handle.net/2117/10951 Title: Location of hot spots in integrated circuits by monitoring the substrate thermal-phase lag with the mirage effect Authors: Perpiñà, Xavier; Altet Sanahujes, Josep; Jordà, Xavier; Vellvehi, Miquel; Mestres, Narcís Abstract: This Letter presents a solution for locating hot spots in active integrated circuits (IC) and devices. This method is based on sensing the phase lag between the power periodically dissipated by a device integrated in an IC (hot spot) and its corresponding thermal gradient into the chip substrate by monitoring the heat-induced refractive index gradient with a laser beam. The experimental results show a high accuracy and prove the suitability of this technique to locate and characterize devices behaving as hot spots in current IC technologies. 2011-01-11T11:22:04Z http://hdl.handle.net/2117/10920 Title: Four different approaches for the measurement of IC surface temperature: Application to thermal testing Authors: Saulnier, J B; Altet Sanahujes, Josep; Dilhaire, S; Volz, S; Rampnoux, J M; Rubio Sola, Jose Antonio; Grauby, S; Patino, L; Claeys, W Abstract: Silicon die surface temperature can be used to monitor the health state of digital and analogue integrated circuits (IC). In the present paper, four different sensing techniques: scanning thermal microscope, laser reflectometer, laser interferometer and electronic built-in differential temperature sensors are used to measure the temperature at the surface of the same IC containing heat sources (hot spots) that behave as faulty digital gates. The goal of the paper is to describe the techniques as well as to present the performances of these sensing methods for the detection and localisation of hot spots in an IC. q 2002 Elsevier Science Ltd All rights reserved. 2011-01-07T12:59:55Z