http://hdl.handle.net/2117/3124 2013-05-23T20:07:58Z http://hdl.handle.net/2117/17192 Title: Teaching engineering with autonomous learning tools: good practices in GRAPAU-RIMA Authors: Marcé Nogué, Jordi; Salán Ballesteros, Maria Núria; Aragoneses Aguado, Andrés; Bernat Masó, Ernest; Escrig Pérez, Christian; Otero Calviño, Beatriz; Rupérez de Gracia, Elisa; Illescas Fernandez, Silvia 2013-01-04T11:39:40Z http://hdl.handle.net/2117/16601 Title: Economic model of a cloud provider operating in a federated cloud Authors: Goiri Presa, Íñigo; Guitart Fernández, Jordi; Torres Viñals, Jordi Abstract: Resource provisioning in Cloud providers is a challenge because of the high variability of load over time. On the one hand, the providers can serve most of the requests owning only a restricted amount of resources, but this forces to reject customers during peak hours. On the other hand, valley hours incur in under-utilization of the resources, which forces the providers to increase their prices to be profitable. Federation overcomes these limitations and allows providers to dynamically outsource resources to others in response to demand variations. Furthermore, it allows providers with underused resources to rent them to other providers. Both techniques make the provider getting more profit when used adequately. Federation of Cloud providers requires having a clear understanding of the consequences of each decision. In this paper, we present a characterization of providers operating in a federated Cloud which helps to choose the most convenient decision depending on the environment conditions. These include when to outsource to other providers, rent free resources to other providers (i.e., insourcing), or turn off unused nodes to save power. We characterize these decisions as a function of several parameters and implement a federated provider that uses this characterization to exploit federation. Finally, we evaluate the profitability of using these techniques using the data from a real provider. 2012-10-03T09:12:30Z http://hdl.handle.net/2117/16287 Title: Implementing end-to-end register data-flow continuous self-test Authors: Carretero Casado, Javier Sebastián; Chaparro, Pedro; Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; González Colás, Antonio María Abstract: While Moore's Law predicts the ability of semiconductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in that law. One concern is the verification effort of modern computing systems, which has grown to dominate the cost of system design. On the other hand, technology scaling leads to burn-in phase out. As a result, in-the-field error rate may increase due to both actual errors and latent defects. Whereas data can be protected with arithmetic codes, there is a lack of cost-effective mechanisms for control logic. This paper presents a light-weight microarchitectural mechanism that ensures that data consumed through registers are correct. The structures protected include the issue queue logic and the data associated (i.e., tags and control signals), input multiplexors, rename data, replay logic, register free-list and release logic, and register file logic. Our results show a coverage around 90 percent for the targeted structures with a cost in power and area of about four percent, and without impact in performance. 2012-07-18T10:36:54Z http://hdl.handle.net/2117/16067 Title: Energy-efficient and multifaceted resource management for profit-driven virtualized data centers Authors: Goiri Presa, Íñigo; Berral García, Josep Lluís; Fitó, Josep Oriol; Julià Massó, Ferran; Nou Castell, Ramon; Guitart Fernández, Jordi; Gavaldà Mestre, Ricard; Torres Viñals, Jordi Abstract: As long as virtualization has been introduced in data centers, it has been opening new chances for resource management. Nowadays, it is not just used as a tool for consolidating underused nodes and save power; it also allows new solutions to well-known challenges, such as heterogeneity management. Virtualization helps to encapsulate Web-based applications or HPC jobs in virtual machines (VMs) and see them as a single entity which can be managed in an easier and more efficient way. We propose a new scheduling policy that models and manages a virtualized data center. It focuses on the allocation of VMs in data center nodes according to multiple facets to optimize the provider’s profit. In particular, it considers energy efficiency, virtualization overheads, and SLA violation penalties, and supports the outsourcing to external providers. The proposed approach is compared to other common scheduling policies, demonstrating that a provider can improve its benefit by 30% and save power while handling other challenges, such as resource outsourcing, in a better and more intuitive way than other typical approaches do. 2012-06-16T10:58:35Z http://hdl.handle.net/2117/16041 Title: Supporting CPU-based guarantees in cloud SLAs via resource-level QoS metrics Authors: Goiri Presa, Íñigo; Julià Masso, Ferran; Fitó, Josep Oriol; Macías Lloret, Mario; Guitart Fernández, Jordi Abstract: Success of Cloud computing requires that both customers and providers can be confident that signed Service Level Agreements (SLA) are supporting their respective business activities to their best extent. Currently used SLAs fail in providing such confidence, especially when providers outsource resources to other providers. These resource providers typically support very simple metrics like availability, or metrics that hinder an efficient exploitation of their resources. In this paper, we propose a resource-level metric for specifying fine-grain guarantees on CPU performance. This metric allows resource providers to allocate dynamically their resources among running services depending on their demand. This is accomplished by incorporating the customer’s CPU usage in the metric definition, but avoiding fake SLA violations when the customer’s task does not use all its allocated resources. We have conducted the evaluation in a virtualized provider where we have implemented the needed infrastructure for using our metric. As demonstrated in our evaluation, our solution presents fewer SLA violations than other CPU-related metrics while maintaining the Quality of Service. 2012-06-14T11:42:36Z http://hdl.handle.net/2117/15645 Title: On the simulation of large-scale architectures using multiple application abstraction levels Authors: Rico Carro, Alejandro; Cabarcas, Felipe; Villavieja Prados, Carlos; Pavlovic, Milan; Vega, Augusto; Etsion, Yoav; Ramírez Bellido, Alejandro; Valero Cortés, Mateo Abstract: Simulation is a key tool for computer architecture research. In particular, cycle-accurate simulators are extremely important for microarchitecture exploration and detailed design decisions, but they are slow and, so, not suitable for simulating large-scale architectures, nor are theymeant for this. Moreover,microarchitecture design decisions are irrelevant, or even misleading, for early processor design stages and high-level explorations. This allows one to raise the abstraction level of the simulated architecture, and also the application abstraction level, as it does not necessarily have to be represented as an instruction stream. In this paper we introduce a definition of different application abstraction levels, and how these are employed in TaskSim, a multi-core architecture simulator, to provide several architecture modeling abstractions, and simulate large-scale architectures with hundreds of cores. We compare the simulation speed of these abstraction levels to the ones in existing simulation tools, and also evaluate their utility and accuracy. Our simulations show that a very high-level abstraction, which may be even faster than native execution, is useful for scalability studies on parallel applications; and that just simulating explicit memory transfers, we achieve accurate simulations for architectures using non-coherent scratchpad memories, with just a 25xslowdown compared to native execution. Furthermore, we revisit trace memory simulation techniques, that are more abstract than instruction-by-instruction simulations and provide an 18x simulation speedup. 2012-03-22T12:17:59Z http://hdl.handle.net/2117/13576 Title: ACOTES project: Advanced compiler technologies for embedded streaming Authors: Duranton, M.; Munk, H.; Ayguadé Parra, Eduard; Bastoul, C.; Carpenter, Paul; Chamski, Z.; Cohen, A.; Cornero, M.; Dumont, P.; Pop, S.; Pop, A.; Ornstein, A.; Nuzman, D.; Miranda, C.; Martorell Bofill, Xavier; Lindwer, M.; Ladelsky, R.; Ferrer, Roger; Fellahi, M.; Pouchet, L. N; Zaks, A.; Shvadron, U.; Trifunovic, K.; Rohou, E.; Rosen, I.; Ramírez Bellido, Alejandro; Ródenas, D. Abstract: Streaming applications are built of data-driven, computational components, consuming and producing unbounded data streams. Streaming oriented systems have become dominant in a wide range of domains, including embedded applications and DSPs. However, programming efficiently for streaming architectures is a challenging task, having to carefully partition the computation and map it to processes in a way that best matches the underlying streaming architecture, taking into account the distributed resources (memory, processing, real-time requirements) and communication overheads (processing and delay). These challenges have led to a number of suggested solutions, whose goal is to improve the programmer’s productivity in developing applications that process massive streams of data on programmable, parallel embedded architectures. StreamIt is one such example. Another more recent approach is that developed by the ACOTES project (Advanced Compiler Technologies for Embedded Streaming). The ACOTES approach for streaming applications consists of compiler-assisted mapping of streaming tasks to highly parallel systems in order to maximize cost-effectiveness, both in terms of energy and in terms of design effort. The analysis and transformation techniques automate large parts of the partitioning and mapping process, based on the properties of the application domain, on the quantitative information about the target systems, and on programmer directives. This paper presents the outcomes of the ACOTES project, a 3-year collaborative work of industrial (NXP, ST, IBM, Silicon Hive, NOKIA) and academic (UPC, INRIA, MINES ParisTech) partners, and advocates the use of Advanced Compiler Technologies that we developed to support Embedded Streaming. 2011-10-18T18:03:13Z http://hdl.handle.net/2117/13460 Title: OPTIMIS: A holistic approach to cloud service provisioning Authors: Badia Sala, Rosa Maria; Juan, Ana; Hernández, Francisco; Tordsson, Johan; Elmroth, Erik; Ali-Eldin, Ahmed; Zsigri, Csilla; Sirvent Pardell, Raül; Guitart Fernández, Jordi; Wesner, Stefan; Kipp, Alexander; Hudzia, Benoit; Varvarigou, Theodora; Konstanteli, Kleopatra; Kousiouris, George; Nair, Srijith K.; Dimitrakos, Theo; Ziegler, Wolfgang; Djemame, Karim; Corrales, Marcelo; Sheridan, Craig; Forgó, Nikolaus; Sharif, Tabassum Abstract: We present fundamental challenges for scalable and dependable service platforms and architectures that enable flexible and dynamic provisioning of cloud services. Our findings are incorporated in a toolkit targeting the cloud service and infrastructure providers. The innovations behind the toolkit are aimed at optimizing the whole service life cycle, including service construction, deployment, and operation, on a basis of aspects such as trust, risk, eco-efficiency and cost. Notably, adaptive self-preservation is crucial to meet predicted and unforeseen changes in resource requirements. By addressing the whole service life cycle, taking into account several cloud architectures, and by taking a holistic approach to sustainable service provisioning, the toolkit aims to provide a foundation for a reliable, sustainable, and trustful cloud computing industry. 2011-10-10T09:34:34Z http://hdl.handle.net/2117/13117 Title: Simulating whole supercomputer applications Authors: González García, Juan; Casas, Marc; Giménez Lucas, Judit; Moreto Planas, Miquel; Ramírez Bellido, Alejandro; Labarta Mancho, Jesús José; Valero Cortés, Mateo Abstract: Detailed simulations of large scale message-passing interface parallel applications are extremely time consuming and resource intensive. A new methodology that combines signal processing and data mining techniques plus a multilevel simulation reduces the simulated data by various orders of magnitude. This reduction makes possible detailed software performance analysis and accurate performance predictions in a reasonable time. 2011-08-25T11:09:46Z http://hdl.handle.net/2117/13110 Title: Hybrid transactional memory with pessimistic concurrency control Authors: Vallejo, Enrique; Sanyal, Sutirtha; Harris, Tim; Vallejo, Fernando; Beivide, Ramón; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo Abstract: Transactional Memory (TM) intends to simplify the design and implementation of the shared-memory data structures used in parallel software. Many Software TM systems are based on writer-locks to protect the data being modified. Such implementations can suffer from the “privatization” problem, in which transactional and non-transactional accesses to the same location can lead to inconsistent results. One solution is the use of Pessimistic Concurrency Control, but it entails an important performance penalty due to the need of reader-writer locking. In this paper a hybrid TM design is proposed to reduce the performance overheads caused by the use of these locks while combining three desirable features: i) full TM functionality whether or not the architectural support is present; ii) execution of a single common code path in software or hardware; and, iii) immunity from the privatization problem. The analysis shows how a Hybrid TM can lose important properties, such as starvation freedom. To overcome this issue, Directory Reservations is presented, a low-cost mechanism improving existent solutions designed for Hardware TM. 2011-08-25T09:51:58Z http://hdl.handle.net/2117/12966 Title: Strategies of Domain Decomposition to Partition Mesh-Based Applications onto Computational Grids Authors: Otero Calviño, Beatriz; Gil, Marisa Abstract: In this paper, we evaluate strategies of domain decomposition in Grid environment to solve mesh-basedapplications. We compare the balanced distribution strategy with unbalanced distribution strategies. While the former is acommon strategy in homogenous computing environment (e.g. parallel computers), it presents some problems due tocommunication latency in Grid environments. Unbalanced decomposition strategies consist of assigning less workload toprocessors responsible for sending updates outside the host. The results obtained in Grid environments show that unbalanceddistributions strategies improve the expected execution time of mesh-based applications by up to 53%. However, this is not truewhen the number of processors devoted to communication exceeds the number of processors devoted to calculation in thehost. To solve this problem we propose a new unbalanced distribution strategy that improves the expected execution time up to43%. We analyze the influence of the communication patterns on execution times using the Dimemas simulator. 2011-07-13T17:33:11Z http://hdl.handle.net/2117/12659 Title: A discrete optimization problem in local networks and data alignment Authors: Fiol Mora, Miquel Àngel; Andrés Yebra, José Luis; Alegre de Miguel, Ignacio; Valero Cortés, Mateo Abstract: This paper presents the solution of the following optimization problem that appears in the design of double-loop structures for local networks and also in data memory, allocation and data alignment in SIMD processors. Consider the digraph on N vertices, labeled from 0 to N - 1, where every vertex i is adjacent to the vertices (i + a) mod Nand (i + b) mod N. How should a and b be chosen in order to minimize the diameter and/or the average distance between vertices of the digraph? The study shows that for every N there are several different solutions (a, b) that produce the minimum values of the diameter and average distance between vertices. These values are of the order of V3 and (5/9 )3N_, respectively. For most values of N there exists a solution with a = 1 that facilitates the implementation of a double-loop structure from a single-loop one. The geometrical approach used to characterize the optimal solutions greatly facilitates the study of routing, throughput, and reliability questions. 2011-05-26T11:53:16Z http://hdl.handle.net/2117/12654 Title: Reduction of connections for multibus organization Authors: Lang, Tomás; Valero Cortés, Mateo; Fiol Mora, Miquel Àngel Abstract: The multibus interconnection network is an attractive solution for connecting processors and memory modules in a multiprocessor with shared memory. It provides a throughput which is intermediate between the single bus and the crossbar, with a corresponding intermediate cost. 2011-05-26T11:02:29Z http://hdl.handle.net/2117/10760 Title: Archexplorer for automatic design space exploration Authors: Desmet, V.; Girbal, Sylvain; Ramírez Bellido, Alejandro; Temam, Olivier; Vega, Augusto Abstract: Growing architectural complexity and stringent time-to-market constraints suggest the need to move architecture design beyond parametric exploration to structural exploration. ArchExplorer is a Web-based permanent and open design-space exploration framework that lets researchers compare their designs against others. The authors demonstrate their approach by exploring the design space of an on-chip memory subsystem and a multicore processor. 2010-12-27T15:31:14Z http://hdl.handle.net/2117/10688 Title: The SARC architecture Authors: Gaydadjiev, Georgi; Isaza, Sebastian; Ramírez Bellido, Alejandro; Cabarcas, Felipe; Juurlink, Ben; Álvarez Mesa, Mauricio; Sánchez Castaño, Friman; Azevedo, Arnaldo; Meenderinck, Cor; Ciobanu, Catalin Abstract: The SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically allocates tasks on the heterogeneous cores and schedules the data transfers through the DMA engines. SARC's programming model supports various highly parallel applications, with matching support from specialized accelerator processors. 2010-12-20T16:21:01Z