http://hdl.handle.net/2117/3114 2013-05-21T09:32:43Z http://hdl.handle.net/2117/19158 Title: DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support Authors: Pavlou, Demos; Gibert Codina, Enric; Latorre, Fernando; González Colás, Antonio María Abstract: Dynamic Binary Translators (DBT) and Dynamic Binary Opti- mization (DBO) by software are used widely for several reasons including performance, design simplification and virtualization. However, the software layer in such systems introduces non- negligible overheads which affect performance and user experi- ence. Hence, reducing DBT/DBO overheads is of paramount im- portance. In addition, reduced overheads have interesting collateral effects in the rest of the software layer, such as allowing optimiza- tions to be applied earlier. A cost-effective solution to this problem is to provide hardware support to speed up the primitives of the software layer, paying special attention to automate DBT/DBO mechanisms and leave the heuristics to the software, which is more flexible. In this work, we have characterized the overheads of a DBO sys- tem using DynamoRIO implementing several basic optimizations. We have seen that the computation of the Data Dependence Graph (DDG) accounts for 5%-10% of the execution time. For this rea- son, we propose to add hardware support for this task in the form of a new functional unit, called DDGacc, which is integrated in a conventional pipeline processor and is operated through new ISA instructions. Our evaluation shows that DDGacc reduces the cost of computing the DDG by 32x, which reduces overall execution time by 5%-10% on average and up to 18% for applications where the DBO optimizes large code footprints. 2013-05-10T12:30:37Z http://hdl.handle.net/2117/18455 Title: A Novel variation-tolerant 4T-DRAM with enhance soft-error tolerance Authors: Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Enrico; González Colás, Antonio María; Rubio Sola, Jose Antonio Abstract: In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. The retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment. 2013-03-21T13:41:03Z http://hdl.handle.net/2117/18448 Title: Analysis of CPI variance for dynamic binary translators/optimizers modules Authors: Brankovic, Aleksandar; Stavrou, Kyriakos; Gibert Codina, Enric; González Colás, Antonio María Abstract: Dynamic Binary Translators and Optimizers (DBTOs) have been established as a hot research topic. They are used in many different systems, such as emulation, instrumentation tools and innovative HW/SW co-designed microarchitectures. Although many researchers worked on characterizing and reducing the emulation overhead, to the best of our knowledge, there are no published results that explain how the microarchitectural behavior of the emulation software is affected by the guest application which is emulated. In this paper we study the DBTO as an independent application, which is divided into the modules with specific functionality. We show the variance in microarchitectural behavior of DBTO among 48 applications. Moreover, we locate and explain the sources of variance. The results show that the variance is caused by interaction with the code cache (emulated application) and non uniform module execution characteristics. The insights presented in this paper can be exploited towards the design of more efficient DBTOs 2013-03-20T19:11:15Z http://hdl.handle.net/2117/18242 Title: Setting an error detection infrastructure with low cost acoustics wave detectors Authors: Upasani, Gaurang; Vera Rivera, Francisco Javier; González Colás, Antonio María Abstract: The continuing decrease in dimensions and operating voltage of transistors has increased their sensitivity against radiation phenomena making soft errors an important challenge in future chip multiprocessors (CMPs). Hence, new techniques for detecting errors in the logic and memories that allow meeting the desired failures-in-time (FIT) budget in CMPs are required. This paper proposes a low-cost dynamic particle strike detection mechanism through acoustic wave detectors. Our results show that our mechanism can protect both the logic and the memory arrays. As a case study, we also show how this technique can be combined with error codes to protect the last-level cache at low cost. 2013-03-12T18:17:30Z http://hdl.handle.net/2117/18207 Title: Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs Authors: Jaksic, Zoran; Canal Corretger, Ramon Abstract: In this paper, we pr esent the dynamic 3T memory cell for future 10nm tri-gate FinFETs as a potential replacement for classical 6T SRAM cell for implementation in high speed cache memories. We investigate read access time, retention time, and static power consumption of the cell when it is exposed to the effects of process and environmental variations. Process variations are extracted from the ITRS predictions and they are modeled at device level. For simulation, we use 10nm SOI tri-gate FinFET BSIM-CMG model card developed by the University of Glasgow, Device Modeling Group. When compared to the classical 6T SRAM, 3T cell has 40% smaller area, leakage is reduced up to 14 times while access time is approximately the same. In order to achieve higher retention times, we propose several cell extensions which, at the same time, enable post- fabrication/run-time adaptability. 2013-03-12T13:17:05Z http://hdl.handle.net/2117/18176 Title: A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance Authors: Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Enrico; González Colás, Antonio María; Rubio Sola, Jose Antonio Abstract: In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. The retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment 2013-03-11T14:33:59Z http://hdl.handle.net/2117/18025 Title: Reducing energy consumption in human-centric wireless sensor networks Authors: Meseguer Pallarès, Roc; Molina Clemente, Carlos; Ochoa, Sergio; Santos, Rodrigo Abstract: Energy consumption is a main research issue in wireless sensor networks; and particularly in those where nodes collaborate to reach a goal. This article explores the energy consumption in mobile devices participating in a human-based wireless sensor network. Specifically, the paper proposes the use of a message predictor to help detect and reduce the number of unnecessary control packets delivered by the nodes as a way to keep updated the network topology. In order to evaluate this proposal, the Optimized Link State Routing protocol was modified to add a message predictor between the routing and the network layers. Eleven simulations were performed using a particular setting. The preliminary results indicate the use of the message predictor can help reduce considerably the nodes energy consumption without affecting the routing capability of the protocol. Although these results are still preliminary, they are highly encouraging. 2013-02-28T17:25:11Z http://hdl.handle.net/2117/16300 Title: A take-home exam to assess professional skills Authors: López Álvarez, David; Cruz Díaz, Josep Llorenç; Sánchez Carracedo, Fermín; Fernández Jiménez, Agustín Abstract: Professional Skills, such as the ability to communicate effectively or the ability to gather and integrate information, are not easy to teach or to assess. A traditional exam is not the best way of assessing these skills because it is limited both by time and by the resources students are able to consult. Moreover, in a traditional exam it is difficult to assess if professional skills have been acquired in depth. In this paper we propose to substitute the traditional exam by a take-home exam in which students have more time to solve the questions and are not restricted by the sources they can consult, thereby providing a highly educational task in which students experience a deep learning process. We also analyze what kind of questions should be asked to evaluate professional skills, as well as analyzing the potential drawbacks of these kind of exams (such as inappropriate student behavior). Finally, we show the results of one subject at the Barcelona School of Informatics, in which the take-home exam replaced the traditional exam. This course has been taught over 11 terms with good results. 2012-07-19T10:15:35Z http://hdl.handle.net/2117/15703 Title: Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study Authors: González Colás, Antonio María; Pons Solé, Marc; Barajas Ojeda, Enrique; Mateo Peña, Diego; López González, Juan Miguel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier Abstract: Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated costs, is studied for a Delay-Locked Loop design (DLL). The comparison with a full custom design demonstrates that VCTA can be used without loss of functionality while accelerating the design time. Layout implementations, in 90 nm CMOS process, as well as the delay, energy and jitter electrical simulations are provided. 2012-04-03T18:06:02Z http://hdl.handle.net/2117/15702 Title: Design of complex circuits using the via-configurable transistor array regular layout fabric Authors: Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María Abstract: Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new method for regular layout generation with Via-Configurable Transistor Arrays focusing on reducing the area overhead associated to regularity. Results for ISCAS85 benchmarks in the 45nm technology node are provided showing that comparable areas to the standard cell approach can be obtained. 2012-04-03T15:06:22Z http://hdl.handle.net/2117/15652 Title: Hardware/software-based diagnosis of load-store queues using expandable activity logs Authors: Carretero Casado, Javier Sebastián; Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; Ramírez García, Tanausu; Monchiero, Matteo; González Colás, Antonio María Abstract: The increasing device count and design complexity are posing significant challenges to post-silicon validation. Bug diagnosis is the most difficult step during post-silicon validation. Limited reproducibility and low testing speeds are common limitations in current testing techniques. Moreover, low observability defies full-speed testing approaches. Modern solutions like on-chip trace buffers alleviate these issues, but are unable to store long activity traces. As a consequence, the cost of post-Si validation now represents a large fraction of the total design cost. This work describes a hybrid post-Si approach to validate a modern load-store queue. We use an effective error detection mechanism and an expandable logging mechanism to observe the microarchitectural activity for long periods of time, at processor full-speed. Validation is performed by analyzing the log activity by means of a diagnosis algorithm. Correct memory ordering is checked to root the cause of errors. 2012-03-22T14:35:06Z http://hdl.handle.net/2117/15651 Title: A co-designed HW/SW approach to general purpose program acceleration using a programmable functional unit Authors: Deb, Abhishek; Codina Viñas, Josep M.; González Colás, Antonio María Abstract: In this paper, we propose a novel programmable functional unit (PFU) to accelerate general purpose application execution on a modern out-of-order x86 processor in a complexity-effective way. Code is transformed and instructions are generated that run on the PFU using a co-designed virtual machine (Cd-VM). Groups of frequently executed micro-operations (micro-ops) are identified and fused into a macro-op (MOP) by the Cd-VM. The MOPs are executed on PFU. Results presented in this paper show that this HW/SW co-designed approach produces average speedups in performance of 17% in SPECFP and 10% in SPECINT, and up-to 33%, over modern out-of-order processor. Moreover, we also show that the proposed scheme not only out-performs dynamic vectorization using SIMD accelerators but also outperforms an 8-wide issue out-of-order processor. 2012-03-22T14:19:30Z http://hdl.handle.net/2117/15648 Title: Fg-STP: fine-grain single thread partitioning on multicores Authors: Ranjan, Rakesh; Latorre Salinas, Fernando; Marcuello Pascual, Pedro; González Colás, Antonio María Abstract: Power and complexity issues have led the microprocessor industry to shift to Chip Multiprocessors in order to be able to better utilize the additional transistors ensured by Moore's law. While parallel programs are going to be able to take most of the advantage of these CMPs, single thread applications are not equipped to benefit from them. In this paper we propose Fine-Grain Single-Thread Partitioning (Fg-STP), a hardware-only scheme that takes advantage of CMP designs to speedup single-threaded applications. Our proposal improves single thread performance by reconfiguring two cores with the aim of collaborating on the fetching and execution of the instructions. These cores are basically conventional out-of-order cores in which execution is orchestrated using a dedicated hardware that has minimum and localized impact on the original design of the cores. This approach partitions the code at instruction granularity and differs from previous proposals on the extensive use of dependence speculation, replication and communication. These features are combined with the ability to look for parallelism on large instruction windows without any software intervention (no re-compilation or profiling hints are needed). These characteristics allow Fg-STP to speedup single thread by 18% and 7% on average over similar hardware-only approaches like Core Fusion, on medium sized and small sized 2-core CMP respectively for Spec 2006 benchmarks. 2012-03-22T12:55:41Z http://hdl.handle.net/2117/14433 Title: Impact of positive bias temperature instability (PBTI) Authors: Aymerich Capdevila, Nivard; Ganapathy, Shrikanth; Rubio Sola, Jose Antonio; Canal Corretger, Ramon; González Colás, Antonio María Abstract: Memory circuits are playing a key role in complex multicore systems with both data and instructions storage and mailbox communication functions. There is a general concern that conventional SRAM cell based on the 6T structure could exhibit serious limitations in future CMOS technologies due to the instability caused by transistor mismatching as well as for leakage consumption reasons. For L1 data caches the new cell 3T1D DRAM is considered a potential candidate to substitute 6T SRAMs. We first evaluate the impact of the positive bias temperature instability, PBTI, on the access and retention time of the 3T1D memory cell implemented with 45 nm technology. Then, we consider all sources of variations and the effect of the degradation caused by the aging of the device on the yield at system level. 2012-01-09T16:07:39Z http://hdl.handle.net/2117/13872 Title: Global productiveness propagation: A code optimization technique to speculatively prune useless narrow computations Authors: Bhagat, Indu; Gibert Codina, Enric; Sanchez, Jesus; González Colás, Antonio María Abstract: This paper proposes a unique hardware-software collaborative strategy to remove useless work at 16-bit data-width granularity. The underlying motivation is to design a low power execution platform by exploiting ‘narrow’ computations. The proposal uses a strictly narrow bit-wide microarchitecture (16-bit integer datapath), which realizes the goal of a low cost, low hardware complexity, low power execution engine. Software dynamically maps the 64-bit computations by translating them into an equivalent 16-bit instruction stream and optimizing them. In this paper, we propose an optimization technique, called Global Productiveness Propagation (GPP), which is a dynamic, profile-based optimization technique that infers the minimum required dataflow by pruning narrow computations that are mostprobably useless (non-productive). More precisely, GPP speculatively prunes the static backward slices of selected narrow computations: computations that result in the same value (in their respective storage location) as that at the input of the region. This speculative optimization technique is formulated around the concept of ‘narrow’ computations because the same allow a finer granularity to distinguish between useful (productive) and useless (nonproductive) work. GPP has been evaluated on an in-order narrow bit-wide execution core, achieving an average dynamic instruction stream reduction of 6.6%, while improving overall performance by 4.2%. 2011-11-13T10:48:24Z