http://hdl.handle.net/2117/3112 2013-05-20T08:51:19Z http://hdl.handle.net/2117/18906 Title: The contribution of Type IA supernovae to the galactic iron abundances Authors: Bravo Guil, Eduardo; Isern Vilaboy, Jordi; Canal Corretger, Ramon Abstract: The thermonuclear explosion of a mass-accreting white dwarf in a close binary system is thought to be at the origin of Type Ia supernovae. Standard models, which ignite carbon at densities higher than 2-4 x 10 exp 9 g/cu cm, give, however, a large production of species like Fe-54, Ni-58, and Cr-54, which has been regarded as incompatible with the solar system abundances. In this paper we analyze the weight of the constraints imposed by nucleosynthesis of the Fe-peak nuclides to the aforementioned scenario for Type Ia supernovae when the contribution of Type II and Type Ib supernovae to the galactic iron abundances is also taken into account. We find that the production of the aforementioned nuclides predicted by standard SNIa models is in fact compatible with the solar system abundances when the yields from gravitational-collapse supernovae are adjusted to reproduce the Ni abundances in low-metallicity stars. 2013-04-19T17:11:40Z http://hdl.handle.net/2117/18905 Title: On the photometric homogeneity of type IA supernovae Authors: Bravo Guil, Eduardo; Domínguez, Inmaculada; Isern, Jordi; Canal Corretger, Ramon; Höflich, P.; Labay, Javier Abstract: The dependence of the characteristics of the light curves of Type Ia supernovae on the ignition density of the progenitor white dwarf is studied with the aid of two models of propagation of the thermonuclear burning front: as a deflagration and as a delayed detonation. The light curve is computed from opacities which take into account the velocity gradients. The results show that in all cases the resulting light curves roughly agree with observations and that they are not sensitive to the ignition density of the white dwarf. Only the model corresponding to a deflagration starting at a density of 8 x 10 exp 9 g/cu cm shows a deviation from the general behavior, having a significantly lower luminosity at maximum. A dispersion of about 1000 km/s is found in the computed expansion velocities at maximum, which compares well with that found in the observations. 2013-04-19T17:02:57Z http://hdl.handle.net/2117/16508 Title: The migration prefetcher: anticipating data promotion in dynamic NUCA caches Authors: Lira Rueda, Javier; Jones, Timothy M.; Molina, Carlos; González Colás, Antonio María 2012-09-17T11:56:24Z http://hdl.handle.net/2117/16287 Title: Implementing end-to-end register data-flow continuous self-test Authors: Carretero Casado, Javier Sebastián; Chaparro, Pedro; Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; González Colás, Antonio María Abstract: While Moore's Law predicts the ability of semiconductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in that law. One concern is the verification effort of modern computing systems, which has grown to dominate the cost of system design. On the other hand, technology scaling leads to burn-in phase out. As a result, in-the-field error rate may increase due to both actual errors and latent defects. Whereas data can be protected with arithmetic codes, there is a lack of cost-effective mechanisms for control logic. This paper presents a light-weight microarchitectural mechanism that ensures that data consumed through registers are correct. The structures protected include the issue queue logic and the data associated (i.e., tags and control signals), input multiplexors, rename data, replay logic, register free-list and release logic, and register file logic. Our results show a coverage around 90 percent for the targeted structures with a cost in power and area of about four percent, and without impact in performance. 2012-07-18T10:36:54Z http://hdl.handle.net/2117/16283 Title: TRAMS Project: variability and reliability of SRAM memories in sub-22nm bulk-CMOS technologies Authors: Canal Corretger, Ramon; Rubio Sola, Jose Antonio; ASenov, Asen; Brown, Andrew; Miranda, Miguel; Zuber, Paul; González Colás, Antonio María; Vera, Xavier Abstract: The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13 nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells and circuits. 2012-07-17T17:48:46Z http://hdl.handle.net/2117/10906 Title: The velox transactional memory stack Authors: Cristal Kestelman, Adrián; Felber, Pascal; Riviere, Etienne; Moreira, Walter Maldonado; Harmanci, Derin; Marlier, Patrick; Diestelhorst, Stephan; Hohmuth, Michael; Pohlack, Martin; Afek, Yehuda; Tomic, Saša; Drepper, Ulrich; Gramoli, Vincent; Kapalka, Michal; Guerraoui, Rachid; Dragojevic, Aleksandar; Stenstrom, Per; Unsal, Osman Sabri; Hur, Ibrahim; Korland, Guy; Nowack, Martin; Riegel, Torvald; Shavit, Nir; Fetzer, Christof Abstract: The transactional memory programming paradigm could become the coordination methodology of choice for actual and future multicore and many-core architectures. The transactional memory support spans a complete software and hardware stack, including programming language and hardware support, runtime and libraries, compilers, and application environments. The VELOX project has developed such a comprehensive transactional memory stack. 2011-01-04T13:11:17Z http://hdl.handle.net/2117/7924 Title: Selective replication: a lightweight technique for soft errors Authors: Vera, Xavier; Abella Ferrer, Jaume; Carretero Casado, Javier Sebastián; González Colás, Antonio María Abstract: Soft errors are an important challenge in contemporary microprocessors. Modern processors have caches and large memory arrays protected by parity or error detection and correction codes. However, today’s failure rate is dominated by flip flops, latches, and the increasing sensitivity of combinational logic to particle strikes. Moreover, as Chip Multi-Processors (CMPs) become ubiquitous, meeting the FIT budget for new designs is becoming a major challenge. Solutions based on replicating threads have been explored deeply; however, their high cost in performance and energy make them unsuitable for current designs. Moreover, our studies based on a typical configuration for a modern processor show that focusing on the top 5 most vulnerable structures can provide up to 70% reduction in FIT rate. Therefore, full replication may overprotect the chip by reducing the FIT much below budget. We propose Selective Replication, a lightweight-reconfigurable mechanism that achieves a high FIT reduction by protecting the most vulnerable instructions with minimal performance and energy impact. Low performance degradation is achieved by not requiring additional issue slots and reissuing instructions only during the time window between when they are retirable and they actually retire. Coverage can be reconfigured online by replicating only a subset of the instructions (the most vulnerable ones). Instructions’vulnerability is estimated based on the area they occupy and the time they spend in the issue queue. By changing the vulnerability threshold, we can adjust the trade-off between coverage and performance loss. Results for an out-of-order processor configured similarly to Intel® CoreTM Micro-Architecture show that our scheme can achieve over 65% FIT reduction with less than 4% performance degradation with small area and complexity overhead. 2010-06-30T13:10:52Z http://hdl.handle.net/2117/7881 Title: Reducing soft errors through operand width aware policies Authors: Ergin, Oguz; Unsal, Osman Sabri; Vera Rivera, Francisco Javier; González Colás, Antonio María Abstract: Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. In this paper, we propose simple mechanisms that effectively reduce the vulnerability to soft errors in a processor. Our designs are generally motivated by the fact that many of the produced and consumed values in the processors are narrow and their upper order bits are meaningless. Soft errors caused by any particle strike to these higher order bits can be avoided by simply identifying these narrow values. Alternatively, soft errors can be detected or corrected on the narrow values by replicating the vulnerable portion of the value inside the storage space provided for the upper order bits of these operands. As a faster but less fault tolerant alternative to ECC and parity, we offer a variety of schemes that make use of narrow values and analyze their efficiency in reducing soft error vulnerability of different data-holding components of a processor. On average, techniques that make use of the narrowness of the values can provide 49 percent error detection, 45 percent error correction, or 27 percent error avoidance coverage for single bit upsets in the first level data cache across all Spec2K. In other structures such as the immediate field of the issue queue, an average error detection rate of 64 percent is achieved. 2010-06-29T10:22:01Z