http://hdl.handle.net/2117/3111 2013-05-23T10:39:37Z http://hdl.handle.net/2117/19158 Title: DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support Authors: Pavlou, Demos; Gibert Codina, Enric; Latorre, Fernando; González Colás, Antonio María Abstract: Dynamic Binary Translators (DBT) and Dynamic Binary Opti- mization (DBO) by software are used widely for several reasons including performance, design simplification and virtualization. However, the software layer in such systems introduces non- negligible overheads which affect performance and user experi- ence. Hence, reducing DBT/DBO overheads is of paramount im- portance. In addition, reduced overheads have interesting collateral effects in the rest of the software layer, such as allowing optimiza- tions to be applied earlier. A cost-effective solution to this problem is to provide hardware support to speed up the primitives of the software layer, paying special attention to automate DBT/DBO mechanisms and leave the heuristics to the software, which is more flexible. In this work, we have characterized the overheads of a DBO sys- tem using DynamoRIO implementing several basic optimizations. We have seen that the computation of the Data Dependence Graph (DDG) accounts for 5%-10% of the execution time. For this rea- son, we propose to add hardware support for this task in the form of a new functional unit, called DDGacc, which is integrated in a conventional pipeline processor and is operated through new ISA instructions. Our evaluation shows that DDGacc reduces the cost of computing the DDG by 32x, which reduces overall execution time by 5%-10% on average and up to 18% for applications where the DBO optimizes large code footprints. 2013-05-10T12:30:37Z http://hdl.handle.net/2117/18906 Title: The contribution of Type IA supernovae to the galactic iron abundances Authors: Bravo Guil, Eduardo; Isern Vilaboy, Jordi; Canal Corretger, Ramon Abstract: The thermonuclear explosion of a mass-accreting white dwarf in a close binary system is thought to be at the origin of Type Ia supernovae. Standard models, which ignite carbon at densities higher than 2-4 x 10 exp 9 g/cu cm, give, however, a large production of species like Fe-54, Ni-58, and Cr-54, which has been regarded as incompatible with the solar system abundances. In this paper we analyze the weight of the constraints imposed by nucleosynthesis of the Fe-peak nuclides to the aforementioned scenario for Type Ia supernovae when the contribution of Type II and Type Ib supernovae to the galactic iron abundances is also taken into account. We find that the production of the aforementioned nuclides predicted by standard SNIa models is in fact compatible with the solar system abundances when the yields from gravitational-collapse supernovae are adjusted to reproduce the Ni abundances in low-metallicity stars. 2013-04-19T17:11:40Z http://hdl.handle.net/2117/18905 Title: On the photometric homogeneity of type IA supernovae Authors: Bravo Guil, Eduardo; Domínguez, Inmaculada; Isern, Jordi; Canal Corretger, Ramon; Höflich, P.; Labay, Javier Abstract: The dependence of the characteristics of the light curves of Type Ia supernovae on the ignition density of the progenitor white dwarf is studied with the aid of two models of propagation of the thermonuclear burning front: as a deflagration and as a delayed detonation. The light curve is computed from opacities which take into account the velocity gradients. The results show that in all cases the resulting light curves roughly agree with observations and that they are not sensitive to the ignition density of the white dwarf. Only the model corresponding to a deflagration starting at a density of 8 x 10 exp 9 g/cu cm shows a deviation from the general behavior, having a significantly lower luminosity at maximum. A dispersion of about 1000 km/s is found in the computed expansion velocities at maximum, which compares well with that found in the observations. 2013-04-19T17:02:57Z http://hdl.handle.net/2117/18455 Title: A Novel variation-tolerant 4T-DRAM with enhance soft-error tolerance Authors: Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Enrico; González Colás, Antonio María; Rubio Sola, Jose Antonio Abstract: In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. The retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment. 2013-03-21T13:41:03Z http://hdl.handle.net/2117/18448 Title: Analysis of CPI variance for dynamic binary translators/optimizers modules Authors: Brankovic, Aleksandar; Stavrou, Kyriakos; Gibert Codina, Enric; González Colás, Antonio María Abstract: Dynamic Binary Translators and Optimizers (DBTOs) have been established as a hot research topic. They are used in many different systems, such as emulation, instrumentation tools and innovative HW/SW co-designed microarchitectures. Although many researchers worked on characterizing and reducing the emulation overhead, to the best of our knowledge, there are no published results that explain how the microarchitectural behavior of the emulation software is affected by the guest application which is emulated. In this paper we study the DBTO as an independent application, which is divided into the modules with specific functionality. We show the variance in microarchitectural behavior of DBTO among 48 applications. Moreover, we locate and explain the sources of variance. The results show that the variance is caused by interaction with the code cache (emulated application) and non uniform module execution characteristics. The insights presented in this paper can be exploited towards the design of more efficient DBTOs 2013-03-20T19:11:15Z http://hdl.handle.net/2117/18242 Title: Setting an error detection infrastructure with low cost acoustics wave detectors Authors: Upasani, Gaurang; Vera Rivera, Francisco Javier; González Colás, Antonio María Abstract: The continuing decrease in dimensions and operating voltage of transistors has increased their sensitivity against radiation phenomena making soft errors an important challenge in future chip multiprocessors (CMPs). Hence, new techniques for detecting errors in the logic and memories that allow meeting the desired failures-in-time (FIT) budget in CMPs are required. This paper proposes a low-cost dynamic particle strike detection mechanism through acoustic wave detectors. Our results show that our mechanism can protect both the logic and the memory arrays. As a case study, we also show how this technique can be combined with error codes to protect the last-level cache at low cost. 2013-03-12T18:17:30Z http://hdl.handle.net/2117/18207 Title: Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs Authors: Jaksic, Zoran; Canal Corretger, Ramon Abstract: In this paper, we pr esent the dynamic 3T memory cell for future 10nm tri-gate FinFETs as a potential replacement for classical 6T SRAM cell for implementation in high speed cache memories. We investigate read access time, retention time, and static power consumption of the cell when it is exposed to the effects of process and environmental variations. Process variations are extracted from the ITRS predictions and they are modeled at device level. For simulation, we use 10nm SOI tri-gate FinFET BSIM-CMG model card developed by the University of Glasgow, Device Modeling Group. When compared to the classical 6T SRAM, 3T cell has 40% smaller area, leakage is reduced up to 14 times while access time is approximately the same. In order to achieve higher retention times, we propose several cell extensions which, at the same time, enable post- fabrication/run-time adaptability. 2013-03-12T13:17:05Z http://hdl.handle.net/2117/18176 Title: A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance Authors: Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Enrico; González Colás, Antonio María; Rubio Sola, Jose Antonio Abstract: In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. The retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment 2013-03-11T14:33:59Z http://hdl.handle.net/2117/18025 Title: Reducing energy consumption in human-centric wireless sensor networks Authors: Meseguer Pallarès, Roc; Molina Clemente, Carlos; Ochoa, Sergio; Santos, Rodrigo Abstract: Energy consumption is a main research issue in wireless sensor networks; and particularly in those where nodes collaborate to reach a goal. This article explores the energy consumption in mobile devices participating in a human-based wireless sensor network. Specifically, the paper proposes the use of a message predictor to help detect and reduce the number of unnecessary control packets delivered by the nodes as a way to keep updated the network topology. In order to evaluate this proposal, the Optimized Link State Routing protocol was modified to add a message predictor between the routing and the network layers. Eleven simulations were performed using a particular setting. The preliminary results indicate the use of the message predictor can help reduce considerably the nodes energy consumption without affecting the routing capability of the protocol. Although these results are still preliminary, they are highly encouraging. 2013-02-28T17:25:11Z http://hdl.handle.net/2117/16935 Title: Cómo formar ingenieros en informática en la competencia sostenibilidad y compromiso social Authors: Franquesa, David; Cruz Díaz, Josep Llorenç; Álvarez Martínez, Carlos; Sánchez Carracedo, Fermín; Fernández Jiménez, Agustín; López Álvarez, David Abstract: In addition to he technical skills, the new trends in engineering education include the so-called professional skills. These skills are usually hard to teach and to evaluate, and some of them are difficult to include in technical subjects. In this paper, we analyze the "Sustainability and Social Responsibility" skill, an we present several techniques to develop it, both at the comprehension and the application levels according to the Bloom taxonomy. Besides, we also analyze the main requirements in an Educational Institution in order to implement this skill. / En los nuevos planes de estudios hay que desarrollar competencias que resultan novedosas: prácticamente no han sido trabajadas con anterioridad. Cómo enseñarlas y cómo evaluarlas es una preocupación para los diseñadores de los nuevos planes. Este artículo analiza la competencia "Sostenibilidad y Compromiso Social", explicando técnicas para desarrollarla tanto a nivel de comprensión como al de aplicación, según la taxonomía de Bloom, y analiza las condiciones que deben darse en un centro para poder implementar estas técnicas en las asignaturas de su plan de estudios. 2012-11-16T11:04:58Z http://hdl.handle.net/2117/16508 Title: The migration prefetcher: anticipating data promotion in dynamic NUCA caches Authors: Lira Rueda, Javier; Jones, Timothy M.; Molina, Carlos; González Colás, Antonio María 2012-09-17T11:56:24Z http://hdl.handle.net/2117/16300 Title: A take-home exam to assess professional skills Authors: López Álvarez, David; Cruz Díaz, Josep Llorenç; Sánchez Carracedo, Fermín; Fernández Jiménez, Agustín Abstract: Professional Skills, such as the ability to communicate effectively or the ability to gather and integrate information, are not easy to teach or to assess. A traditional exam is not the best way of assessing these skills because it is limited both by time and by the resources students are able to consult. Moreover, in a traditional exam it is difficult to assess if professional skills have been acquired in depth. In this paper we propose to substitute the traditional exam by a take-home exam in which students have more time to solve the questions and are not restricted by the sources they can consult, thereby providing a highly educational task in which students experience a deep learning process. We also analyze what kind of questions should be asked to evaluate professional skills, as well as analyzing the potential drawbacks of these kind of exams (such as inappropriate student behavior). Finally, we show the results of one subject at the Barcelona School of Informatics, in which the take-home exam replaced the traditional exam. This course has been taught over 11 terms with good results. 2012-07-19T10:15:35Z http://hdl.handle.net/2117/16287 Title: Implementing end-to-end register data-flow continuous self-test Authors: Carretero Casado, Javier Sebastián; Chaparro, Pedro; Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; González Colás, Antonio María Abstract: While Moore's Law predicts the ability of semiconductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in that law. One concern is the verification effort of modern computing systems, which has grown to dominate the cost of system design. On the other hand, technology scaling leads to burn-in phase out. As a result, in-the-field error rate may increase due to both actual errors and latent defects. Whereas data can be protected with arithmetic codes, there is a lack of cost-effective mechanisms for control logic. This paper presents a light-weight microarchitectural mechanism that ensures that data consumed through registers are correct. The structures protected include the issue queue logic and the data associated (i.e., tags and control signals), input multiplexors, rename data, replay logic, register free-list and release logic, and register file logic. Our results show a coverage around 90 percent for the targeted structures with a cost in power and area of about four percent, and without impact in performance. 2012-07-18T10:36:54Z http://hdl.handle.net/2117/16283 Title: TRAMS Project: variability and reliability of SRAM memories in sub-22nm bulk-CMOS technologies Authors: Canal Corretger, Ramon; Rubio Sola, Jose Antonio; ASenov, Asen; Brown, Andrew; Miranda, Miguel; Zuber, Paul; González Colás, Antonio María; Vera, Xavier Abstract: The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13 nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells and circuits. 2012-07-17T17:48:46Z http://hdl.handle.net/2117/15703 Title: Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study Authors: González Colás, Antonio María; Pons Solé, Marc; Barajas Ojeda, Enrique; Mateo Peña, Diego; López González, Juan Miguel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier Abstract: Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated costs, is studied for a Delay-Locked Loop design (DLL). The comparison with a full custom design demonstrates that VCTA can be used without loss of functionality while accelerating the design time. Layout implementations, in 90 nm CMOS process, as well as the delay, energy and jitter electrical simulations are provided. 2012-04-03T18:06:02Z