Exploració per tema "jitter"
Ara es mostren els items 3-4 de 4
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Design of a clock and data recovery circuit in FDSOI technology for high speed serial links
(Universitat Politècnica de Catalunya, 2021-03)
Projecte Final de Màster Oficial
Accés obertThe purpose of this thesis is to design an 8 Gbps clock and data recovery circuit intended to work in the receiver of a high-speed Serializer-Deserializer interface (SerDes). The proposed architecture is based on a ... -
Threshold and timing errors of 1 bit / 2 level digital correlators in earth observation synthetic aperture radiometry
(IEE-INST ELEC ENG, 1997-04-30)
Article
Accés obertAnalytical expressions for the errors generated in 1 bit/2-level digital correlators (IB/2L) are derived: threshold errors in comparators and timing (skew and jitter) errors in samplers. These expressions are used to specify ...