Exploració per tema "jitter"
Ara es mostren els items 1-4 de 4
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A web interface for wireless mesh networks based on heuristic algorithms: optimisation and analysis for different scenarios
(2015-07)
Article
Accés restringit per política de l'editorialIn this work, we present WMN-HC and WMN-SA systems which are based on Hill Climbing (HC) and Simulated Annealing (SA) for location assignment of mesh routers in Wireless Mesh Networks (WMNs). As evaluation metrics, we used ... -
CMOS Law-jitter Clock Driver Design
(Universitat Politècnica de Catalunya, 2012-09)
Projecte Final de Màster Oficial
Accés obert[ANGLÈS] Design of a low-jitter, low-phase noise clock driver in 40 nm CMOS technology. The work is in the field of analog integrated circuit (IC) design in nanometer CMOS technologies. -
Design of a clock and data recovery circuit in FDSOI technology for high speed serial links
(Universitat Politècnica de Catalunya, 2021-03)
Projecte Final de Màster Oficial
Accés obertThe purpose of this thesis is to design an 8 Gbps clock and data recovery circuit intended to work in the receiver of a high-speed Serializer-Deserializer interface (SerDes). The proposed architecture is based on a ... -
Threshold and timing errors of 1 bit / 2 level digital correlators in earth observation synthetic aperture radiometry
(IEE-INST ELEC ENG, 1997-04-30)
Article
Accés obertAnalytical expressions for the errors generated in 1 bit/2-level digital correlators (IB/2L) are derived: threshold errors in comparators and timing (skew and jitter) errors in samplers. These expressions are used to specify ...