Exploració per tema "Timing analysis"
Ara es mostren els items 6-7 de 7
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Ring oscillator clocks and margins
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertHow much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA ... -
Using randomized caches in probabilistic real-time systems
(2009)
Text en actes de congrés
Accés restringit per política de l'editorialWhile hardware caches are generally effective at improving application performance, they greatly complicate performance prediction. Slight changes in memory layout or data access patterns can lead to large and ...