Exploració per tema "Timing"

Ara es mostren els items 44-47 de 47

    • Verification of concurrent systems with parametric delays using octahedra 

      Clarisó Viladrosa, Robert; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2005)
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      A technique for the verification of concurrent parametric timed systems is presented. In the systems under study, each action has a bounded delay where the bounds are either constants or parameters. Given a safety property, ...

    • Verification of timed circuits with symbolic delays 

      Clarisó Viladrosa, Robert; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2004)
      Text en actes de congrés
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      Verifying timed circuits is a complex problem even when the delays of the system are fixed. This paper deals with a more challenging problem, the formal verification of timed circuits with unspecified delays represented ...

    • What is the cost of delay insensitivity? 

      Saito, Hiroshi; Kondratyev, Alex; Cortadella, Jordi; Lavagno, Luciano; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1999)
      Text en actes de congrés
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      Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous speed-independent (SI) circuits, whose behaviour ...

    • Work-in-Progress Paper: An Analysis of the Impact of Dependencies on Probabilistic Timing Analysis and Task Scheduling 

      Mezzetti, Enrico; Abella Ferrer, Jaume; Hernandez, Carles; Cazorla, Francisco J. (IEEE, 2018-02-01)
      Comunicació de congrés
      Accés obert
      Recently there has been a renewed interest for probabilistic timing analysis (PTA) and probabilistic task scheduling (PTS). Despite the number of works in both fields, the link between them is weak: works on the latter ...