Exploració per tema "Timing"
Ara es mostren els items 38-47 de 47
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Robust data detection in asynchronous DS-CDMA in the presence of timing uncertainty
(IEEE, 1996)
Text en actes de congrés
Accés obertThe decorrelating and minimum mean squared error data detectors for direct sequence code division multiple access (DS-CDMA) communications systems are known to exhibit low vulnerability to the near-far problem. Nevertheless, ... -
SAFEXPLAIN: Safe and Explainable Critical Embedded Systems Based on AI
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Comunicació de congrés
Accés obertDeep Learning (DL) techniques are at the heart of most future advanced software functions in Critical Autonomous AI-based Systems (CAIS), where they also represent a major competitive factor. Hence, the economic success ... -
Seeking time-composable partitions of tasks for COTS multicore processors
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Comunicació de congrés
Accés obertThe timing verification of real-time single core systems involves a timing analysis step that yields an Execution Time Bound (ETB) for each task, followed by a schedulability analysis step, where the scheduling attributes ... -
Synchronous elastic networks
(Institute of Electrical and Electronics Engineers (IEEE), 2006)
Text en actes de congrés
Accés obertWe formally define - at the stream transformer level - a class of synchronous circuits that tolerate any variability in the latency of their environment. We study behavioral properties of networks of such circuits and prove ... -
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertThis paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ensure functionality. Relative timing assumptions ... -
Time-constrained loop pipelining
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertThis paper addresses the problem of Time-Constrained Loop Pipelining, i.e. given a fixed throughput, finding a schedule of a loop which minimizes resource requirements. We propose a methodology, called TCLP, based on ... -
Verification of concurrent systems with parametric delays using octahedra
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertA technique for the verification of concurrent parametric timed systems is presented. In the systems under study, each action has a bounded delay where the bounds are either constants or parameters. Given a safety property, ... -
Verification of timed circuits with symbolic delays
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertVerifying timed circuits is a complex problem even when the delays of the system are fixed. This paper deals with a more challenging problem, the formal verification of timed circuits with unspecified delays represented ... -
What is the cost of delay insensitivity?
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertDeep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous speed-independent (SI) circuits, whose behaviour ... -
Work-in-Progress Paper: An Analysis of the Impact of Dependencies on Probabilistic Timing Analysis and Task Scheduling
(IEEE, 2018-02-01)
Comunicació de congrés
Accés obertRecently there has been a renewed interest for probabilistic timing analysis (PTA) and probabilistic task scheduling (PTS). Despite the number of works in both fields, the link between them is weak: works on the latter ...
