Ara es mostren els items 19-38 de 47

    • Formal verification of safety properties in timed circuits 

      Peña Basurto, Marco Antonio; Cortadella, Jordi; Kondratyev, Alex; Pastor Llorens, Enric (Institute of Electrical and Electronics Engineers (IEEE), 2000)
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      The incorporation of timing makes circuit verification computationally expensive. This paper proposes a new approach for the verification of timed circuits. Rather than calculating the exact timed stare space, a conservative ...
    • Hardware schemes for early register release 

      Monreal Arnal, Teresa; Viñals Yufera, Víctor; González Colás, Antonio María; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2002)
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      Register files are becoming one of the critical components of current out-of-order processors in terms of delay and power consumption, since their potential to exploit instruction-level parallelism is quite related to the ...
    • Impact of the mechanical interface on BCG signals obtained from electronic weighing scales 

      Casanella Alonso, Ramón; Gómez Clapers, Joan; Hernández Urrea, Marc; Pallàs-Areny, Ramon (2016)
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      Accés restringit per política de l'editorial
      This work analyzes the reproducibility of the BCG obtained from different weighing scales. First, the natural frequency of three commercial bathroom scales has been characterized by an impulse excitation test. Second, the ...
    • Improving the Front-end Performance of a Time Randomised Processor for Hard Real-Time Systems 

      Rufart Blasco, Eric (Universitat Politècnica de Catalunya, 2023-10-20)
      Projecte Final de Màster Oficial
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      In Hard Real-time Systems, the execution of tasks must be completed within a certain timeframe, known as deadline. In consequence, when a hard-real time system is designed, it is strictly necessary to assume that its tasks ...
    • Increasing the Reliability of Software Timing Analysis for Cache-Based Processors 

      Milutinovic, Suzana; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla, Francisco J. (IEEE, 2019-06-01)
      Article
      Accés obert
      Real-time systems are witnessing a significant increase in critical software's size, complexity, and performance needs, which can only be satisfied with high-performance hardware features. Cache memories, pervasively used ...
    • Lazy transition systems: application to timing optimization of asynchronous circuits 

      Cortadella, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Taubin, Alexander; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1998)
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      The paper introduces Lazy Transitions Systems (LzTSs). The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. LzTSs can be effectively used to model the ...
    • Maximum-Contention Control Unit (MCCU): Resource Access Count and Contention Time Enforcement 

      Cardona, Jordi; Hernandez, Carles; Abella Ferrer, Jaume; Cazorla, Francisco J. (IEEE, 2019-04-16)
      Comunicació de congrés
      Accés obert
      In real-time systems, the techniques to derive bounds to the contention tasks can suffer in multicore build on resource quota monitoring and enforcement. Existing techniques track and bound the number of requests to hardware ...
    • Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study 

      Wartel, Franck; Kosmidis, Leonidas; Lo, Code; Triquet, Benoit; Quiñones, Eduardo; Abella Ferrer, Jaume; Gogonel, Adriana; Baldovin, Andrea; Mezzetti, Enrico; Cucu Grosjean, Liliana; Vardanega, Tulio; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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      Accés restringit per política de l'editorial
      Probabilistic Timing Analysis (PTA) in general and its measurement-based variant called MBPTA in particular can mitigate some of the problems that impair current worst-case execution time (WCET) analysis techniques. MBPTA ...
    • Measuring the tolerance of self-adaptive clocks to supply voltage noise 

      Pérez Puigdemont, Jordi; Moll Echeto, Francisco de Borja; Cortadella, Jordi (2011)
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      Simultaneous switching noise has become an important issue due to its signal integrity and timing implications. Therefore a lot of time and resources are spent during the PDN design to minimize the supply voltage variation. ...
    • Modelling bus contention during system early design stages 

      Trilla, David; Hernandez, Carles; Abella Ferrer, Jaume; Cazorla, Francisco J. (IEEE, 2017-07-31)
      Comunicació de congrés
      Accés obert
      Reliably upperbounding contention in multicore shared resources is of prominent importance in the early design phases of critical real-time systems to properly allocate time budgets to applications. However, during early ...
    • Modelling the confidence of timing analysis for time randomised caches 

      Benedicte Illescas, Pedro; Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Text en actes de congrés
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      Timing is a key non-functional property in embedded real-Time systems (ERTS). ERTS increasingly require higher levels of performance that can only be sensibly provided by deploying high-performance hardware, which however ...
    • Motor tèrmic Berdrod 

      Bernet Duque, Marc-Teodor (Universitat Politècnica de Catalunya, 2019-07)
      Treball Final de Grau
      Accés obert
      Estudi de la viabilitat d’una variant del motor de combustió interna alternatiu de quatre temps destinat a vehicles, principalment motocicletes, que combina la adequació metamòrfica de la funcionalitat dels elements que ...
    • Multi-level dataflow-driven macro placement guided by RTL structure and analytical methods 

      Vidal Obiols, Alexandre; Cortadella, Jordi; Petit Silvestre, Jordi; Galcerán Oms, Marc; Martorell Cid, Ferran (2021-12)
      Article
      Accés obert
      When RTL designers define the hierarchy of a system, they exploit their knowledge about the conceptual abstractions devised during the design and the functional interactions between the logical components. This valuable ...
    • Multicore Early Design Stage Guaranteed Performance Estimates for the Space Domain 

      Fernandez, Mikel; Fernandez, Gabriel; Abella Ferrer, Jaume; Cazorla, Francisco J. (IEEE, 2019-05-16)
      Comunicació de congrés
      Accés obert
      The ability to produce early guaranteed performance (worst-case execution time) estimates for multicores, i.e. before software from different providers gets integrated onto the same critical system, is pivotal. This helps ...
    • Non-data-aided frequency offset and symbol timing estimation for binary CPM: performance bounds 

      Riba Sagarra, Jaume; Vázquez Grau, Gregorio (Institute of Electrical and Electronics Engineers (IEEE), 2000)
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      The use of (spectrally efficient) CPM modulations may lead to a serious performance degradation of the classical non-data-aided (NDA) frequency and timing estimators due to the presence of self noise. The actual performance ...
    • On uses of extreme value theory fit for industrial-quality WCET analysis 

      Milutinovic, Suzana; Mezzetti, Enrico; Abella Ferrer, Jaume; Vardanega, Tullio; Cazorla, Francisco J. (IEEE, 2017-07-31)
      Comunicació de congrés
      Accés obert
      Over the last few years, considerable interest has arisen in measurement-based probabilistic timing analysis. The term MBPTA has been used to indistinctly refer to a variety of different applications of Extreme Value Theory ...
    • Positioning and timing in the MIMO-gnss framework 

      García Molina, J. A.; Fernández Rubio, Juan Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      This paper discusses about GNSS-based positioning and timing in challenging propagation conditions for receivers featuring an array of antennas with an arbitrary distribution. In particular, the positioning and timing ...
    • Probabilistic timing analysis on time-randomized platforms for the space domain 

      Fernandez, Mikel; Morales, David; Kosmidis, Leonidas; Bardizbanyan, Alen; Broster, Ian; Hernandez, Carles; Quiñones, Eduardo; Abella Ferrer, Jaume; Cazorla, Francisco; Machado, Paulo; Fossati, Luca (Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
      Comunicació de congrés
      Accés obert
      Timing Verification is a fundamental step in real-time embedded systems, with measurement-based timing analysis (MBTA) being the most common approach used to that end. We present a Space case study on a real platform that ...
    • pTNoC: Probabilistically time-analyzable tree-based NoC for mixed-criticality systems 

      Slijepcevic, Mladen; Fernández, Mikel; Hernández, Carles; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Text en actes de congrés
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      The use of networks-on-chip (NoC) in real-time safety-critical multicore systems challenges deriving tight worst-case execution time (WCET) estimates. This is due to the complexities in tightly upper-bounding the contention ...
    • Robust data detection in asynchronous DS-CDMA in the presence of timing uncertainty 

      Riba Sagarra, Jaume; Goldberg, J; Vázquez Grau, Gregorio (IEEE, 1996)
      Text en actes de congrés
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      The decorrelating and minimum mean squared error data detectors for direct sequence code division multiple access (DS-CDMA) communications systems are known to exhibit low vulnerability to the near-far problem. Nevertheless, ...