Exploració per tema "Timing"
Ara es mostren els items 7-26 de 47
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Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis
(IEEE, 2017-09-28)
Comunicació de congrés
Accés obertWormhole-based NoCs (wNoCs) are widely accepted in high-performance domains as the most appropriate solution to interconnect an increasing number of cores in the chip. However, wNoCs suitability in the context of critical ... -
Bridging modularity and optimality: delay-insensitive interfacing in asynchronous circuits synthesis
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertTwo trends are of major concern for digital circuit designers: the relative increase of interconnect delays with respect to gate delays and the demand for design reuse. Both pose difficult problems to synchronous design ... -
CAD directions for high performance asynchronous circuits
(Association for Computing Machinery (ACM), 1999)
Text en actes de congrés
Accés obertThis paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using relative timing. This methodology was developed for a prototype iA32 ... -
Challenges in deeply heterogeneous high performance systems
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés obertRECIPE (REliable power and time-ConstraInts-aware Predictive management of heterogeneous Exascale systems) is a recently started project funded within the H2020 FETHPC programme, which is expressly targeted at exploring ... -
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Text en actes de congrés
Accés restringit per política de l'editorialWith every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits. Propagation delays which decide circuit ... -
Conditional maximum likelihood timing recovery: estimators and bounds
(IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2001-04-30)
Article
Accés obertThis paper is concerned with the derivation of new estimators and performance bounds for the problem of timing estimation of (linearly) digitally modulated signals. The conditional maximum likelihood (CML) method is adopted, ... -
Coping with the variability of combinational logic delays
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertThis paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on dual-rail encoding, and guarantees low timing overhead ... -
Desarrollo de actividades de un módulo profesional de preimpresión digital
(Universitat Politècnica de Catalunya, 2017-06-21)
Projecte Final de Màster Oficial
Accés restringit per acord de confidencialitat -
Design and implementation of a fair credit-based bandwidth sharing scheme for buses
(Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
Comunicació de congrés
Accés obertFair arbitration in the access to hardware shared resources is fundamental to obtain low worst-case execution time (WCET) estimates in the context of critical real-time systems, for which performance guarantees are essential. ... -
Dynamic software randomisation: Lessons learnec from an aerospace case study
(2017-05-15)
Comunicació de congrés
Accés obertTiming Validation and Verification (V&V) is an important step in real-time system design, in which a system's timing behaviour is assessed via Worst Case Execution Time (WCET) estimation and scheduling analysis. For WCET ... -
EPC Enacted: Integration in an Industrial Toolbox and Use against a Railway Application
(Institute of Electrical and Electronics Engineers (IEEE), 2017-06-08)
Comunicació de congrés
Accés obertMeasurement-based timing analysis approaches are increasingly making their way into several industrial domains on account of their good cost-benefit ratio. The trustworthiness of those methods, however, suffers from the ... -
EPC: Extended Path Coverage for Measurement-Based Probabilistic Timing Analysis
(IEEE, 2016-01-18)
Comunicació de congrés
Accés obertMeasurement-based probabilistic timing analysis (MBPTA) computes trustworthy upper bounds to the execution time of software programs. MBPTA has the connotation, typical of measurement-based techniques, that the bounds ... -
Formal verification of safety properties in timed circuits
(Institute of Electrical and Electronics Engineers (IEEE), 2000)
Text en actes de congrés
Accés obertThe incorporation of timing makes circuit verification computationally expensive. This paper proposes a new approach for the verification of timed circuits. Rather than calculating the exact timed stare space, a conservative ... -
Hardware schemes for early register release
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Text en actes de congrés
Accés obertRegister files are becoming one of the critical components of current out-of-order processors in terms of delay and power consumption, since their potential to exploit instruction-level parallelism is quite related to the ... -
Impact of the mechanical interface on BCG signals obtained from electronic weighing scales
(2016)
Text en actes de congrés
Accés restringit per política de l'editorialThis work analyzes the reproducibility of the BCG obtained from different weighing scales. First, the natural frequency of three commercial bathroom scales has been characterized by an impulse excitation test. Second, the ... -
Improving the Front-end Performance of a Time Randomised Processor for Hard Real-Time Systems
(Universitat Politècnica de Catalunya, 2023-10-20)
Projecte Final de Màster Oficial
Accés obertIn Hard Real-time Systems, the execution of tasks must be completed within a certain timeframe, known as deadline. In consequence, when a hard-real time system is designed, it is strictly necessary to assume that its tasks ... -
Increasing the Reliability of Software Timing Analysis for Cache-Based Processors
(IEEE, 2019-06-01)
Article
Accés obertReal-time systems are witnessing a significant increase in critical software's size, complexity, and performance needs, which can only be satisfied with high-performance hardware features. Cache memories, pervasively used ... -
Lazy transition systems: application to timing optimization of asynchronous circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Text en actes de congrés
Accés obertThe paper introduces Lazy Transitions Systems (LzTSs). The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. LzTSs can be effectively used to model the ... -
Maximum-Contention Control Unit (MCCU): Resource Access Count and Contention Time Enforcement
(IEEE, 2019-04-16)
Comunicació de congrés
Accés obertIn real-time systems, the techniques to derive bounds to the contention tasks can suffer in multicore build on resource quota monitoring and enforcement. Existing techniques track and bound the number of requests to hardware ... -
Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialProbabilistic Timing Analysis (PTA) in general and its measurement-based variant called MBPTA in particular can mitigate some of the problems that impair current worst-case execution time (WCET) analysis techniques. MBPTA ...
